Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 200

Exceptions
Table 6-7. Register Settings after an Alignment Exception (continued)
Register
MSR POW 0
ILE —
EE 0
PR 0
DSISR 0–14 Cleared
15–16 For instructions that use register indirect with index addressing—set to bits 29–30 of the
instruction encoding.
For instructions that use register indirect with immediate index addressing—cleared
17 For instructions that use register indirect with index addressing—set to bit 25 of the instruction
encoding.
For instructions that use register indirect with immediate index addressing— set to bit 5 of the
instruction encoding.
18–21 For instructions that use register indirect with index addressing—set to bits 21–24 of the
instruction encoding.
For instructions that use register indirect with immediate index addressing—set to bits 1–4 of the
instruction encoding.
22–26 Set to bits 6–10 (identifying either the source or destination) of the instruction encoding.
Undefined for dcbz.
27–31 Set to bits 11–15 of the instruction encoding (rA) for update-form instructions
Set to either bits 11–15 of the instruction encoding or to any register number not in the range of
registers loaded by a valid form instruction for lmw, lswi, and lswx instructions. Otherwise
undefined.
If there is no corresponding instruction, no alternative value can be specified.
DAR Set to the EA of the data access as computed by the instruction causing the alignment exception.
The architecture does not support the use of a misaligned EA by load/store with reservation instructions.
If one of these instructions specifies a misaligned EA, the exception handler should not emulate the
instruction but should treat the occurrence as a programming error.
6.1.2.6.1 Integer Alignment Exceptions
Operations that are not naturally aligned may suffer performance degradation, depending on the processor
design, the type of operation, the boundaries crossed, and the mode that the processor is in during
execution. More specifically, these operations may either cause an alignment exception or they may cause
the processor to break the memory access into multiple, smaller accesses with respect to the cache and the
memory subsystem.
6.1.2.7 Program Exception (0x00700)
A program exception occurs when no higher priority exception exists and one or more of the following
exception conditions, which correspond to bit settings in SRR1, occur during execution of an instruction:
• An lswx instruction for which rA or rB is in the range of registers to be loaded (may cause results
that are boundedly undefined)
• Privileged instruction—A privileged instruction type program exception is generated when the
execution of a privileged instruction is attempted and the processor is operating in user mode
(MSR[PR] is set). It is also generated for mtspr or mfspr instructions that have an invalid SPR
6-8
Setting Description
FP 0
ME —
SE 0
BE 0
MPC885 PowerQUICC Family Reference Manual, Rev. 2
IP — LE
IR 0
DR 0
RI 0
Set to value of ILE
Freescale Semiconductor