Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 947

Priority Source Description
0x1F Parallel I/O–PC15
(Highest)
2
0x1E SCCa (grouped and spread)
2
0x1D SCCb (grouped)
2
0x1C SCCc (grouped)
2
0x1B SCCd (grouped)
0x1A Parallel I/O–PC14
0x19 Timer 1
0x18 Parallel I/O–PC13
0x17 Parallel I/O–PC12
0x16 SDMA channel bus error
0x15 IDMA1
0x14 IDMA2
2
0x13 SCCb (spread)
0x12 Timer 2
0x11 RISC timer table
2
0x10 I C
1
Port C interrupts (external sources) are described in
2
USB and SCCs can be programmed to any of these locations. Group and spread are described in
"Programming Relative Priority (Grouping and Spreading)."
The only true SDMA interrupt source is the SDMA channel bus error entry that is reported when a bus
error occurs during an SDMA access. Other SDMA-related interrupts are reported through each individual
USB, SCC, SMC, SPI, or I
next two sections.
35.2.1 Programming Relative Priority (Grouping and Spreading)
The relative priority between the USB and the 3 SCCs is programmable dynamically through
CICR[SCnP], shown in Table
can be mapped to any of these locations. This is programmed in the CICR (see
SCC entries can be grouped or spread by clearing or setting CICR[SPS], respectively; SPS cannot be
changed dynamically. These options are described as follows:
• If SPS = 1, the USB and 3 SCCs are grouped at the top of the priority table, ahead of most other
CPM interrupt sources. Grouping is useful where the USB and 3 SCCs function at a very high data
rate and interrupt latency is critical.
Freescale Semiconductor
Table 35-1. Prioritization of CPM Interrupt Sources
Multiple
Events
1
No
Yes
Yes
Yes
Yes
1
No
Yes
1
No
1
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Section 34.4.1.5, "Port C Interrupt Control Register (PCINT)."
2
C channel. USB and SCCs interrupts can be reprioritized as described in the
35-3. Table 35-1 has no explicit entry for USB and SCCs because the entries
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Priority Source Description
0x0F Parallel I/O–PC11
0x0E Parallel I/O–PC10
2
0x0D SCCc (spread)
0x0C Timer3
1
0x0B Parallel I/O–PC9
1
0x0A Parallel I/O–PC8
1
0x09 Parallel I/O–PC7
2
0x08 SCCd (spread)
0x07 Timer4
1
0x06 Parallel I/O–PC6
0x05 SPI
0x04 SMC1
0x03 SMC2/PIP
1
0x02 Parallel I/O–PC5
1
0x01 Parallel I/O–PC4
0x00 Reserved
(Lowest)
Table
CPM Interrupt Controller
Multiple
Events
1
No
1
No
Yes
Yes
No
No
No
Yes
Yes
No
Yes
Yes
Yes
No
No
—
Section 35.2.1,
35-3).
35-3