Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 164

MPC8xx Core Register Set
specifically by the PowerPC architecture and is discussed in the Programming Environments
Manual.)
The following situations cause the DAR, BAR, and DSISR registers to be updated.
Table 4-7. Value Summary of the DAR, BAR, and DSISR Registers
Exception Type
DSI
Alignment
Data breakpoint
Machine check
Software emulation exception
Floating-point unavailable
Program exception
4.1.2.2 Unsupported Registers
The MPC885 does not support the following OEA registers:
• DBATs and IBATs —The MPC885 does not support block address translation.
• EAR—The MPC885 does not support the optional external access facility.
• SDR1—The MPC885 does not support memory segments.
• Segment registers—The MPC885 does not support memory segments.
4.1.2.3 PowerPC Supervisor-Level Register Bit Assignments
This section describes bit assignments of supervisor-level PowerPC registers implemented by the
MPC885. For more details, see the Programming Environments Manual for 32-Bit Processors.
4.1.2.3.1 Machine State Register (MSR)
The 32-bit machine state register (MSR) is used to configure such parameters as the privilege level,
whether translation is enabled, and the endian mode. It can be read by the mfmsr instruction and modified
by the mtmsr, sc, and rfi instructions.
4-6
DAR Value
Cycle EA
Data EA
Does not change
Cycle EA
Does not change
Does not change
Does not change
MPC885 PowerQUICC Family Reference Manual, Rev. 2
DSISR Value
Data MMU error status Undefined
Instruction information Undefined
Does not change Cycle EA
Instruction information Undefined
Does not change Undefined
Does not change Undefined
Does not change Does not change
BAR Value
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