Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 782

SCC Transparent Mode
ones, as programmed in GSMR_L[TEND]. The SCC polls the first BD in the TxBD table. When there is
a message to send, the SCC fetches data from memory, loads the transmit FIFO, and waits for transmitter
synchronization, which is achieved with CTS or by waiting for the receiver to achieve synchronization,
depending on GSMR_H[TXSY]. Transmission begins when transmitter synchronization is achieved.
When all BD data has been sent, if TxBD[L] is set, the SCC writes the message status bits into the BD,
clears TxBD[R], and sends idles until the next BD is ready. If it is ready, some idles are still sent. The
transmitter resumes sending only after it achieves synchronization.
If TxBD[L] is cleared when the end of the BD is reached, only TxBD[R] is cleared and the transmitter
moves immediately to the next buffer to begin transmission with no gap on the serial line between buffers.
Failure to provide the next buffer in time causes a transmit underrun which sets SCCE[TXE].
In both cases, an interrupt is issued according to TxBD[I]. By appropriately setting TxBD[I] in each BD,
interrupts are generated after each buffer or group of buffers is sent. The SCC then proceeds to the next
BD in the table and any whole number of bytes can be sent. If GSMR_H[REVD] is set, the bit order of
each byte is reversed before being sent; the msb of each octet is sent first.
Setting GSMR_H[TFL] makes the transmit FIFO smaller and reduces transmitter latency, but it can cause
transmitter under-runs at higher transmission speeds. An optional CRC, selected in GSMR_H[TCRC], can
be appended to each transparent frame if it is enabled in the TxBD.
When the time-slot assigner (TSA) is used with a transparent-mode channel, synchronization is provided
by the TSA. There is a start-up delay for the transmitter, but delays will always be some whole number of
complete TSA frames. This means that n-byte transmit buffers can be mapped directly into n-byte time
slots in the TSA frames.
28.2 SCC Transparent Channel Frame Reception Process
When the core enables the SCC receiver in transparent mode, it waits to achieve synchronization before
data is received. The receiver can be synchronized to the data by a synchronization pulse or SYNC pattern.
After a buffer is full, the SCC clears RxBD[E] and generates a maskable interrupt if RxBD[I] is set. It
moves to the next RxBD in the table and begins moving data to its buffer. If the next buffer is not available,
SCCE[BSY] signifies a busy signal that can generate a maskable interrupt. The receiver reverts to hunt
mode when an
ENTER HUNT MODE
order of each byte is reversed before it is written to memory.
Setting GSMR_H[RFW] reduces receiver latency by making the receive FIFO smaller, which may cause
receiver overruns at higher transmission speeds. The receiver always checks the CRC of the received
frame, according to GSMR_H[TCRC]. If a CRC is not required, resulting errors can be ignored.
28.3 Achieving Synchronization in Transparent Mode
Once the SCC transmitter is enabled for transparent operation, the TxBD is prepared and the transmit FIFO
is pre-loaded by the SDMA channel, another process must occur before data can be sent. It is called
transmit synchronization. Similarly, once the SCC receiver is enabled for transparent operation in the
GSMR and the RxBD is made empty for the SCC, receive synchronization must occur before data can be
28-2
command or an error is received. If GSMR_H[REVD] is set, the bit
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor