Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 841

1
Offset Name Width
0x24 — Word Tx temp. Reserved for CPM use.
0x28 - — —
0x2F
Note: The user must initialize only items in bold.
1
As programmed in SPI_BASE. The default value is IMMR + 0x3D80. See
2
Normally, these parameters need not be accessed. They are listed to help experienced users in debugging.
30.5.1 Receive/Transmit Function Code Registers
(RFCR/TFCR)
Figure 30-9 shows the fields in the receive/transmit function code registers (RFCR/TFCR).
0
Field
Reset
R/W
Addr
Figure 30-9. Receive/Transmit Function Code Registers (RFCR/TFCR)
Table 30-6 describes the RFCR/TFCR fields.
Bits Name
0– — Reserved, should be cleared.
3–4 BO Byte ordering. Set BO to select the required byte ordering for the buffer. If BO is changed on the
fly, it takes effect at the beginning of the next frame or BD. See
00 Reserved
01 Modified little-endian.
1x Big-endian or true little-endian.
5–7 AT[1–3] Address type 1–3. Contains the user-defined function code value used during the SDMA channel
memory access. AT0 is always driven high to identify this channel access as a DMA-type access.
Freescale Semiconductor
Table 30-5. SPI Parameter RAM Memory Map (continued)
2
Used during I C/SPI relocation, see
2
—
SPI Base + 04 (RFCR)/SPI Base + 05 (TFCR)
Table 30-6. RFCR/TFCR Field Descriptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Section 18.7.3, "Parameter RAM."
Section 18.7.3, "Parameter RAM."
3 4 5
BO
0000_0000
R/W
Description
Appendix A, "Byte
Serial Peripheral Interface (SPI)
7
AT[1–3]
Ordering."
30-11