Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 19

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15.6.4.10 The Last Word (LAST)........................................................................................ 15-52
15.6.4.11 The Wait Mechanism (WAEN)............................................................................ 15-52
15.6.4.11.1 Internal and External Synchronous Masters .................................................... 15-52
15.6.4.11.2 External Asynchronous Masters...................................................................... 15-53
15.7 Handling Devices with Slow or Variable Access Times.............................................. 15-54
15.7.1 Hierarchical Bus Interface Example ........................................................................ 15-54
15.7.2 Slow Devices Example ............................................................................................ 15-55
15.8 External Master Support .............................................................................................. 15-55
15.8.1 Synchronous External Masters ................................................................................ 15-55
15.8.2 Asynchronous External Masters .............................................................................. 15-55
15.8.3 Special Case: Address Type Signals for External Masters ...................................... 15-56
15.8.4 UPM Features Supporting External Masters ........................................................... 15-56
15.8.4.1 Address Incrementing for External Synchronous Bursting Masters ................... 15-56
15.8.4.2 Handshake Mechanism for Asynchronous External Masters.............................. 15-56
15.8.4.3 Special Signal for External Address Multiplexer Control ................................... 15-56
15.8.5 External Master Examples ....................................................................................... 15-57
15.8.5.1 External Masters and the GPCM ......................................................................... 15-57
15.8.5.2 External Masters and the UPM............................................................................ 15-58
15.9 Memory System Interface Examples ........................................................................... 15-63
15.9.1 Page-Mode DRAM Interface Example.................................................................... 15-63
15.9.2 Page Mode Extended Data-Out Interface Example................................................. 15-74
16.1 System Configuration .................................................................................................... 16-1
16.2 PCMCIA Module Signal Definitions ............................................................................ 16-1
16.2.1 PCMCIA Cycle Control Signals................................................................................ 16-3
16.2.2 PCMCIA Input Port Signals ...................................................................................... 16-4
16.2.3 PCMCIA Output Port Signals (OP[0:4]) ................................................................... 16-5
16.2.4 Other PCMCIA Signals ............................................................................................. 16-5
16.3 Operation Description.................................................................................................... 16-6
16.3.1 Memory-Only Cards .................................................................................................. 16-6
16.3.2 I/O Cards.................................................................................................................... 16-6
16.3.3 Interrupts.................................................................................................................... 16-7
16.3.4 Power Control ............................................................................................................ 16-7
16.3.5 Reset and Three-State Control ................................................................................... 16-7
16.3.6 DMA .......................................................................................................................... 16-7
16.4 Programming Model ...................................................................................................... 16-8
16.4.1 PCMCIA Interface Input Pins Register (PIPR) ......................................................... 16-8
16.4.2 PCMCIA Interface Status Changed Register (PSCR) ............................................. 16-10
Freescale Semiconductor
Contents
Title
Chapter 16
PCMCIA Interface
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Page
Number
xix