Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 600

SDMA Channels and IDMA Emulation
19.3.7 IDMA Interface Signals—DREQ and SDACK
Each IDMA channel (IDMA1 and IDMA2) has two dedicated control signals—DMA request (DREQ) and
SDMA acknowledge (SDACK). DREQ0 and SDACK1 are dedicated to IDMA1, while DREQ1 and
SDACK2 are for IDMA2.
DREQ and SDACK are the handshake signals between the MPC885 and an external peripheral requesting
service. A peripheral requests IDMA service directly to the CPM by asserting DREQ. When the CPM
begins the transfer, it acknowledges the peripheral by asserting SDACK. A requesting peripheral can either
be the source or the destination of an IDMA transfer. Note that SDACK is not used for memory/memory
transfers.
The following subsections discuss the interface signals used for requesting memory/memory and
peripheral/memory transfers.
19.3.7.1 IDMA Requests for Memory/Memory Transfers
Because there is no internal mechanism, an externally-connected DREQ must still be used to generate
IDMA memory/memory transfer requests. This can be done using a general-purpose I/O line or a
general-purpose timer output.
To use a general-purpose I/O line, follow these steps:
1. Externally connect a general-purpose output line to DREQ.
2. Set RCCR[DRnM] (level-sensitive).
3. Drive the output low when the request generation should begin.
The IDMA controller continuously requests the bus until the current buffer chain is completely transferred.
The transfer terminates with an out-of-buffers error (IDSR[OB]).
To use a general-purpose timer output (TOUTx), follow these steps:
1. Externally connect a TOUTx to DREQ.
2. Clear RCCR[DRnM] (edge-sensitive).
3. Program the timer period to pace the IDMA requests (and thus bus utilization).
An interrupt handler can service the IDSR[DONE] interrupt and suspend the channel; otherwise, the
transfer terminates with an out-of-buffers error (IDSR[OB]).
19.3.7.2 IDMA Requests for Peripheral/Memory Transfers
Once an IDMA channel has been activated, an external peripheral requests a transfer using DREQ. The
user programs the RISC controller (the CP) configuration register (RCCR) to make IDMA requests either
edge- or level-sensitive. The RCCR settings also determine the priority of DREQ relative to the SCCs. See
Section 18.6.1, "RISC Controller Configuration Register (RCCR)."
multiplexed through PC15 and PC14 respectively, the port C pin assignment register and direction register
must be configured as well; see
19-14
Section 34.4, "Port C."
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Since DREQ0 and DREQ1 are
Freescale Semiconductor