Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 261

Table 8-11 describes MD_TWC fields.
Name
Bits
Write Read
0–19 L2TB L2TB
20–22 — L2INDX Ignore
23–26 APG
27 G
28–29 PS
30 WT —
31 V —
8.8.6 IMMU Real Page Number Register (MI_RPN)
The IMMU real page number register (MI_RPN), shown in
the memory attributes of an entry to be loaded into a TLB. MI_RPN should be written after MI_EPN and
MI_TWC are written.
0
Field
Reset
R/W
16
Field RPN
Reset
R/W
SPR
Freescale Semiconductor
Table 8-11. MD_TWC Field Descriptions
Write
Tablewalk level-two table base value
Access protection group. Up to 16 protection groups
are supported. Set to 0000 on a DTLB miss.
Guarded memory attribute of the entry:
0 Nonguarded memory. Cleared on DTLB miss.
1 Guarded memory
Level-one page size. (Cleared on a DTLB miss.)
00 Small (4 Kbyte or 16 Kbyte. See MD_RPN)
01 512 Kbyte
10 Reserved
11 8 Mbyte
Writethrough attribute for page entry:
0 Copyback data cache policy. Cleared on DTLB
miss.
1 Writethrough data cache policy
0 Entry is not valid
1 Entry is valid. (set on a DTLB miss)
19 20
Figure 8-11. IMMU Real Page Number Register (MI_RPN)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Level-two table index. Returns
MD_EPN[10–19] when
MD_CTR[TWAM] = 1
Returns MD_EPN[12–21] when
MD_CTR[TWAM] = 0
Returns 0 on read.
Returns 0 on read
Figure 8-11, contains the physical address and
RPN
—
R/W
27
PP
—
R/W
790
Memory Management Unit
Read
15
28 29 30 31
SPS SH CI V
8-19