Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 671

21.4.6 Clock Glitch Detection
Clock glitches cause problems for many communications systems, and they may go undetected by the
system. Systems that supply an external clock to a serial channel are often susceptible to glitches from
noise, connecting or disconnecting the physical cable from the application board, or excessive ringing on
a clock line. A clock glitch occurs when more than one edge occurs in a time period that violates the
minimum high or low time specification of the input clock.
The SCCs on the MPC885 have a special circuit designed to detect glitches and alert the system of a
problem at the physical layer. The glitch-detect circuit is not a specification test; if a circuit does not meet
the SCC's input clocking specifications, erroneous data may not be detected or false glitch indications can
occur. Regardless of whether the DPLL is used, the received clock is passed through a noise filter that
eliminates any noise spikes that affect a single sample. This sampling is enabled using GSMR_H[GDE].
If a spike is detected, a maskable Rx or Tx glitched clock interrupt is generated in SCCEx[GLR,GLT].
Although the receiver or transmitter can be reset or allowed to continue operation, statistics on clock
glitches should be kept for evaluation to help in debugging, especially during prototype testing.
21.4.7 Reconfiguring the SCCs
The proper reconfiguration sequence must be followed for SCC parameters that cannot be changed
dynamically. For instance, the internal baud rate generators allow on-the-fly changes, but the
DPLL-related GSMR does not. The steps in the following sections show how to disable, reconfigure and
re-enable an SCC to ensure that buffers currently in use are properly closed before reconfiguring the SCC
and that subsequent data goes to or from new buffers according to the new configuration.
Modifying parameter RAM does not require the SCC to be fully disabled. See the parameter RAM
description for when values can be changed. To disable the SCCs, SMCs, SPI, and the I
to reset the entire CPM.
21.4.7.1 General Reconfiguration Sequence for an SCC Transmitter
An SCC transmitter can be reconfigured by following these general steps:
1. If the SCC is sending data, issue a
If the SCC is not transmitting (no TxBDs are ready or the
has been issued and completed) or the
command is not required.
TRANSMIT
2. Clear GSMR_L[ENT] to disable the SCC transmitter and put it in reset state.
3. Modify SCC Tx parameters or parameter RAM. To switch protocols or restore the initial Tx
parameters, issue an
4. If an
INIT TX PARAMETERS
command.
5. Set GSMR_L[ENT]. Transmission begins using the TxBD pointed to by TBPTR, assuming the R
bit is set.
Freescale Semiconductor
STOP TRANSMIT
INIT TX PARAMETERS
command.
INIT TX PARAMETERS
command was not issued in step 3, issue a
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Serial Communications Controllers
command. Transmission should stop smoothly.
GRACEFUL STOP TRANSMIT
command is issued, the
RESTART TRANSMIT
2
C, set CPCR[RST]
command
STOP
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