Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 269

Bits Name
30 PV
31 G
8.8.12.4 DMMU CAM Entry Read Register (MD_CAM)
When the DMMU CAM entry read register (MD_CAM), shown in
effective address and page sizes of an entry indexed by MD_CTR[DTLB_INDX]. This register is updated
when a value is written to it.
0
Field
Reset
R/W
16
Field EPN
Reset
R/W
SPR
Table 8-20 describes MD_CAM fields.
Bits Name
0–19 EPN Effective page number
20 SPVF Subpage validity flags
0 Subpage 0 (address[20–21] = 00) is not valid
1 Subpage 0 (address[20–21] = 00) is valid
21 0 Subpage 1 (address[20–21] = 01) is not valid
1 Subpage 1 (address[20–21] = 01) is valid
22 0 Subpage 2 (address[20–21] = 10) is not valid
1 Subpage 2 (address[20–21] = 10) is valid
23 0 Subpage 3 (address[20–21] = 11) is not valid
1 Subpage 3 (address[20–21] = 11) is valid
Freescale Semiconductor
Table 8-19. MI_RAM1 Field Descriptions (continued)
Page validity
0 Page is not valid
1 Page is valid
Guarded memory attribute for entry
0 Nonguarded memory
1 Guarded memory
19 20
SPVF
Figure 8-20. DMMU CAM Entry Read Register (MD_CAM)
Table 8-20. MD_CAM Field Descriptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Figure 8-20, is read, it contains the
EPN
—
R(/W)
23 24 26 27
PS SH
—
R(/W)
824
Description
Memory Management Unit
15
28 31
ASID
8-27