Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 603

SDMA Channels and IDMA Emulation
T3 T1 T3 T1 T3 T1 T3 T1 T3 T1 T3
CLKOUT
Address
TS
R/W
T
SETUP
T
HOLD
Data
TA
SDACK
T
DELAY
T
PHOLD
Figure 19-10. SDACK Timing Diagram: Single-Address
Peripheral Write, Externally Generated TA
T3 T1 T3 T1 T3 T1 T3 T1 T3 T1 T3
CLKOUT
Address
TS
R/W
T
SETUP
T
HOLD
Data
TA
SDACK
T
DELAY
T
PHOLD
Figure 19-11. SDACK Timing Diagram: Single-Address
Peripheral Write, Internally Generated TA
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 19-17