Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 195

Table 6-1. Offset of First Instruction by Exception Type (continued)
Offset Exception
0x01000 Software emulation
0x01100 Instruction TLB miss
0x01200 Data TLB miss
0x01300 Instruction TLB error
0x01400 Data TLB error
0x01500- Reserved
0x01B00
0x01C00 Data breakpoint
0x01D00 Instruction breakpoint
0x01E00 Peripheral breakpoint
0x01F00 Nonmaskable development port
6.1.1 Exception Ordering
There are two types of exceptions. Instruction-related exceptions (synchronous exceptions) and
asynchronous exceptions (interrupts).
Synchronous exceptions are detected while the core is processing the instruction. These exceptions are
handled in strict program order and cannot be nested. A single instruction may generate multiple
exceptions; however, any subsequent exceptions are not detected until the first exception is handled and
control is returned to the program.
If more than one instruction in the pipeline causes an exception or if one instruction causes multiple
exceptions, the first exception in program order is taken first. Subsequent instructions are flushed and
additional instruction-related exceptions are handled in order.
Typically, asynchronous exceptions are generated by signals or by other hardware conditions.
lists the instruction-related exceptions in the order of detection within the instruction processing.
Number Exception Type
1 Trace
2
2 ITLB miss
2
3 ITLB error
4 Machine check
5 Debug instruction breakpoint
6 Software emulation exception
Freescale Semiconductor
Implementation-Specific Exceptions
See Section 6.1.3.1, "Software Emulation Exception (0x01000)."
See Section 6.1.3.2, "Instruction TLB Miss Exception (0x01100)."
See Section 6.1.3.3, "Data TLB Miss Exception (0x01200)."
See Section 6.1.3.4, "Instruction TLB Error Exception (0x01300)."
See Section 6.1.3.5, "Data TLB Error Exception (0x014000)."
—
See Section 6.1.3.6, "Debug Exceptions (0x01C00–0x01F00)."
Table 6-2. Instruction-Related Exception Detection Order
Trace bit asserted
Instruction MMU TLB miss
Instruction MMU protection/translation error
Fetch error
2
Match detection
2
Attempt to invoke unimplemented feature
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Cause
1
Exceptions
Table 6-2
6-3