Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 251

0
Level-1 Table Pointer (M_TWB)
20-Bit
Level-1 Table Base
20-Bit
20-Bit
20 for 4 Kbyte
18 for 16 Kbyte
13 for 512 Kbyte
Figure 8-4. Two-Level Translation Table (MD_CTR[TWAM] = 1)
When MD_CTR[TWAM] = 1, the tablewalk begins at the level-one base address in M_TWB. EA[0–9]
indicates the level-one page descriptor. As shown in
entries in the level-one table, one for bit 9 = 0 and one for bit 9 = 1.
Table 8-1. Identical Entries Required in Level-One/Level-Two Tables
Identical Entries Required in Level-One Table
Page Size
MD_CTR[TWAM] = 0
1 Kbyte
4 Kbytes
16 Kbytes
512 Kbytes
8 Mbytes
Freescale Semiconductor
19 0
Level-1 Index
Level-1 Index
Level-1 Table
Level-1 Descriptor 0
Level-1 Descriptor 1
Level-1 Descriptor N
Level-1 Descriptor 1023
Level-2 Table Base
20-Bit
Level-2 Descriptor 1023
9 for 8 Mbyte
MD_CTR[TWAM] = 1
1 —
1 1
1 1
1 1
8 2
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Effective Address
9 10
Level-2 Index
10-Bit
00
10-Bit
10-Bit
Level-2 Index
Level-2 Table
10-Bit
Level-2 Descriptor 0
Level-2 Descriptor 1
Level-2 Descriptor N
Physical Page Address
Physical Address
Table 8-1, an 8-Mbyte page requires two identical
Identical Entries Required in Level-Two Table
MD_CTR[TWAM] = 0
1
4
16
1
1
Memory Management Unit
19 20 31
Page Offset
12 for 4 Kbyte
14 for 16 Kbyte
19 for 512 Kbyte
23 for 8 Mbyte
00
Page Offset
MD_CTR[TWAM] = 1
—
1
4
1
1
8-9