Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 661

Powerquicc family

Table of Contents

Function Code Registers (RFCR and TFCR)

Each SCC has two separate function code registers—one for Rx buffers (RFCRx) and one for Tx buffers

(TFCRx). Function code registers contain the value to appear on AT[1–3] when the associated SDMA

channel accesses memory. It also selects the byte-ordering convention.

describes RFCRx/TFCRx fields.

Reserved, should be cleared.

Byte ordering. Program BO to select the required byte ordering for the buffer. If BO is changed on

the fly, it takes effect at the beginning of the next frame (Ethernet, HDLC, and transparent) or at the

beginning of the next BD. See

01 Modified little-endian

1x Big-endian or true little-endian

AT[1–3] Address type. Contains the function code value used during the SDMA channel memory access.

Note AT[0] is driven high to identify this SDMA channel access as a DMA type.

Handling SCC Interrupts

SCC interrupts are handled globally by the CPM interrupt controller (CPIC) using the CPM interrupt

pending register (CIPR), CPM interrupt mask register (CIMR), and CPM in-service register (CISR),

described in

Chapter 35, "CPM Interrupt Controller."

or report individual interrupts in an SCC. Interrupt priority among SCCs is determined in the CPM

interrupt configuration register (CICR).

To allow interrupt handling for SCC-specific events, further event, mask, and status registers are provided

within each SCC's internal memory map area; see

protocol-dependent, event descriptions are found in the specific protocol chapters.

Freescale Semiconductor

SCC x base + 0x04 (RFCR x ); SCC x base + 0x05 (TFCR x )

Figure 21-8. Function Code Registers (RFCR and TFCR)

Table 21-6. RFCR x /TFCR x Field Descriptions

Appendix A, "Byte Ordering."

MPC885 PowerQUICC Family Reference Manual, Rev. 2

Bits in each CPIC register are used to mask, enable,

21-7. Since interrupt events are

Serial Communications Controllers

shows the register