Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 435

This register is affected by HRESET but is not affected by SRESET.
Bits Name
0 — Reserved, should be cleared.
1–2 COM Clock output module. This field controls the output buffer of the CLKOUT pin. When both bits are
set, the CLKOUT pin is held in the high state. These bits can be dynamically changed without
generating spikes on the CLKOUT pin. If the CLKOUT pin is not connected to external circuits,
clock output should be disabled to minimize noise and power dissipation. The COM field is cleared
by hard reset.
00 Clock output enabled full-strength buffer.
01 Reserved.
10 Reserved.
11 Clock output disabled.
3–5 — Reserved, should be cleared.
6 TBS Timebase source. Determines the clock source that drives the timebase and decrementer.
0 Timebase frequency source is the OSCLK divided by 4 or 16.
1 Timebase frequency source is GCLK2 divided by 16.
7 PTDIV Periodic interrupt timer clock divide. Determines if the clock, the crystal oscillator, or main clock
oscillator to the periodic interrupt timer is divided by 4 or 512. At power-on reset this bit is cleared
if the MODCK1 and MODCK2 signals are low.
0 The clock is divided by 4.
1 The clock is divided by 512.
8 PTSEL Periodic interrupt timer select. Selects the crystal oscillator or main clock oscillator as the input
source to PITCLK. At power-on reset, it reflects the value of MODCK1.
0 OSCM (crystal oscillator) is selected.
1 EXTCLK is selected.
9 CRQEN CPM request enable. Cleared by power-on or hard reset. In low-power modes, specifies if the
general system clock returns to high frequency while the CP is active.
0 The system remains in low frequency even if the communication processor module is active.
1 The system switches to high frequency when the communication processor module is active.
10 – Reserved, should be cleared
11–12 — Reserved, should be cleared.
13–14 EBDF External bus division factor. This field defines the frequency division factor between GCLK x and
GCLK x _50. CLKOUT is similar to GCLK2_50. The GCLK x _50 is used by the bus interface and
memory controller to interface with an external system. This field is initialized during hard reset
using the hard reset configuration word in
00 CLKOUT is GCLK2 divided by 1.
01 CLKOUT is GCLK2 divided by 2.
10 Reserved.
11 Reserved.
15–16 — Reserved, should be cleared.
Freescale Semiconductor
Table 14-8. SCCR Field Descriptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Table 14-8
Description
Section 11.3.1.1, "Hard Reset Configuration
Clocks and Power Control
describes SCCR fields.
Word."
14-19