Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 572

Communications Processor
Bits Name
2–7 TIMEP Timer period. Controls the period of the CP's internal timer tick. The RISC timer table are scanned
on each timer tick. The input to the timer tick generator is the system clock divided by 1,024. The
formula is: timer tick period = (TIMEP + 1) × 1,024 system clocks. Thus, a value of 0 stored in this
field creates a timer tick every 1 × (1,024) = 1,024 system clocks; a value of 63 causes a tick every
64 × (1,024) = 65,536 system clocks.
8 DR1M IDMA request 1 mode. Controls the IDMA request 1 (DREQ1) sensitivity mode. See
Section 19.3.7, "IDMA Interface Signals—DREQ and SDACK."
0 DREQ1 is edge-sensitive.
1 DREQ1 is level-sensitive.
9 DR0M IDMA request 0 mode. Controls the IDMA request 0 (DREQ0) sensitivity mode. See
Section 19.3.7, "IDMA Interface Signals—DREQ and SDACK."
0 DREQ0 is edge-sensitive.
1 DREQ0 is level-sensitive.
10–11 DRQP IDMA emulation request priority. Controls the priority of the external request signals that relate to
the serial channels. See
00 IDMA requests have priority over the SCCs and USB.
01 IDMA requests have priority immediately following the SCCs (option 2).
10 IDMA requests have the lowest priority (option 3).
11 Reserved.
12 EIE External interrupt enable. Configure as instructed in the download process of a Freescale-supplied
RAM microcode package.
0 DREQ0 cannot interrupt the CP.
1 DREQ0 will interrupt the CP.
13 SCD Scheduler configuration. Configure as instructed in the download process of a Freescale-supplied
RAM microcode package.
0 Normal operation.
1 Alternate configuration of the scheduler.
14–15 ERAM Enable RAM microcode Configure as instructed in the download process of a Freescale-supplied
microcode package. See
00 Disable microcode program execution in the dual-port system RAM.
01 Microcode executes from the first 512 bytes and a 256-byte extension of dual-port system RAM.
10 Microcode executes from the first 1 Kbyte and a 256-byte extension of dual-port system RAM.
11 Microcode executes from the first 2 Kbytes and a 512-byte extension of dual-port system RAM.
18.6.2 RISC Microcode Development Support Control Register (RMDS)
The RISC microcode development support control register (RMDS), shown in
which regions of the dual-port RAM can contain executable microcode. RMDS is used with
RCCR[ERAM] to determine the valid address space for executable microcode.
RAM and Microcode Packages,"
18-6
Table 18-4. RCCR Field Descriptions (continued)
Section 18.3, "Communicating with the Peripherals."
Section 18.7.1, "System RAM and Microcode Packages."
describes the partitioning of the dual-port system RAM.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Figure 18-4, determines
Section 18.7.1, "System
Freescale Semiconductor