Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 721

MPC885
SCC
6-Bit Sync Two HDLC
TXD
Sequence Flags
RTS
Standard HDLC frame handling
The 16× overspeed of a 3.686-MHz clock can be generated from an external frequency source or from one
of the baud rate generators if the resulting output frequency is close to a multiple of the 3.686 MHz
frequency. The MPC885 asserts RTS throughout the duration of the frame so that RTS can be used to
enable the RS-422 transmit driver.
24.4 Programming the SCC in AppleTalk Mode
The AppleTalk controller is implemented by setting certain bits in the HDLC controller. Otherwise,
Chapter 23, "SCC HDLC Mode,"
TODR to program the AppleTalk controller.
24.4.1 Programming the GSMR
Program the GSMR as described below:
1. Set MODE to 0b0010 (AppleTalk).
2. Set DIAG to 0b00 for normal operation, with CD and CTS grounded or configured for parallel I/O.
This causes CD and CTS to be internally asserted to the SCC.
3. Set RDCR and TDCR to (0b10) a 16× clock.
4. Set the TENC and RENC bits to 0b010 (FM0).
5. Clear TEND for default operation.
6. Set TPP to 0b11 for a preamble pattern of all ones.
7. Set TPL to 0b000 to transmit the next frame with no synchronization sequence and to 001 to
transmit the next frame with the LocalTalk synchronization sequence. For example, data frames do
not require a preceding synchronization sequence. These bits may be modified on the fly if the
AppleTalk protocol is selected.
Freescale Semiconductor
Tx Data
TXD
Tx Enable
RTS
Rx Data
RXD
Stored in Receive Buffer
Stored in Transmit Buffer
Destination Source Control
Address Address Byte
Figure 24-2. Connecting the MPC885 to LocalTalk
describes how to program the HDLC controller. Use GSMR, PSMR, or
MPC885 PowerQUICC Family Reference Manual, Rev. 2
RS-422
MINI-DIN 8
Connection
Closing
Data CRC-16
Flag
SCC AppleTalk Mode
16 Ones
(Abort)
24-3