Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 60

Figure
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2
32-14 I C Transmit Buffer Descriptor (TxBD)............................................................................. 32-13
33-1 PIP Block Diagram ............................................................................................................... 33-2
33-2 PIP Function Code Register (PFCR) .................................................................................... 33-4
33-3 Status Mask Register (SMASK) ........................................................................................... 33-4
33-4 Control Character Table, RCCM, and RCCR ....................................................................... 33-7
33-5 PIP Configuration Register (PIPC) ....................................................................................... 33-8
33-6 PIP Event Register (PIPE) .................................................................................................. 33-10
33-7 PIP Timing Parameters Register (PTPR) ............................................................................ 33-11
33-8 Port B General-Purpose I/O ................................................................................................ 33-11
33-9 PIP Tx Buffer Descriptor (TxBD)....................................................................................... 33-12
33-10 PIP Rx Buffer Descriptor (RxBD) ...................................................................................... 33-13
33-11 Interlocked Handshake Mode Timing................................................................................. 33-15
33-12 Pulsed Handshake Full Cycle ............................................................................................. 33-16
33-13 Pulsed Handshake BUSY Signal ........................................................................................ 33-17
33-14 PIP Transmitter Timing Diagram........................................................................................ 33-18
33-15 PIP Receiver Timing—Mode 0........................................................................................... 33-18
33-16 PIP Receiver Timing—Mode 1........................................................................................... 33-18
33-17 PIP Receiver Timing—Mode 2........................................................................................... 33-18
33-18 PIP Receiver Timing—Mode 3........................................................................................... 33-19
33-19 PIP Transparent Transfers ................................................................................................... 33-19
33-20 The PIP Centronics Interface Signals ................................................................................. 33-20
33-21 PIP as a Centronics Transmitter .......................................................................................... 33-21
33-22 PIP as a Centronics Receiver .............................................................................................. 33-22
34-1 Port A Open-Drain Register (PAODR)................................................................................. 34-4
34-2 Port A Data Register (PADAT) ............................................................................................. 34-4
34-3 Port A Data Direction Register (PADIR).............................................................................. 34-5
34-4 Port A Pin Assignment Register (PAPAR)............................................................................ 34-5
34-5 Block Diagram for PA15 (True for all Non-Open-Drain Port Signals) ................................ 34-6
34-6 Block Diagram for PA14 (True for all Open-Drain Port Signals) ........................................ 34-7
34-7 Port B Open-Drain Register (PBODR) ................................................................................. 34-9
34-8 Port B Data Register (PBDAT) ........................................................................................... 34-10
34-9 Port B Data Direction Register (PBDIR) ............................................................................ 34-10
34-10 Port B Pin Assignment Register (PBPAR).......................................................................... 34-11
34-11 Port C Data Register (PCDAT) ........................................................................................... 34-14
34-12 Port C Data Direction Register (PCDIR) ............................................................................ 34-15
34-13 Port C Pin Assignment Register (PCPAR).......................................................................... 34-15
34-14 Port C Special Options Register (PCSO) ............................................................................ 34-16
34-15 Port C Interrupt Control Register (PCINT)......................................................................... 34-17
34-16 Port D Data Register (PDDAT)........................................................................................... 34-19
34-17 Port D Data Direction Register (PDDIR) ........................................................................... 34-19
34-18 Port D Pin Assignment Register (PDPAR) ........................................................................ 34-20
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Title
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Page
Number
Freescale Semiconductor