Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 445

is used as the RAS signal for 32-bit DRAM with BR1[MS] configured to select UPMA. The BS_A signals
are used as CAS signals on the DRAM.
GPCM
UPMA
The UPMs provide a flexible interface to many types of memory devices. Each UPM can control the
address multiplexing necessary to access DRAM devices, the timing of the BS signals, and the timing of
the GPL signals. Each memory bank can be assigned to either UPM.
Each UPM is a programmable RAM-based machine. The UPM toggles the memory controller external
signals as programmed in RAM when an internal or external master initiates an external single-beat or
burst read/write access. The UPM also controls address multiplexing, address increment, and transfer
acknowledge assertion for each memory access. The UPM specifies a set of signal patterns for a
user-specified number of clock cycles. The UPM RAM pattern run by the memory controller is selected
according to the type of external access transacted. At every clock cycle, the logical value of the external
signals specified in the RAM array is output on the corresponding UPM pins. See
Freescale Semiconductor
MPC885
Address
CS0
GPL1/OE
WE[0:1]
Data
CS1
BS_A[0:3]
R/W
Figure 15-3. Simple System Configuration
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Memory Controller
EPROM
Address
CE
OE
WE
Data
DRAM
Address
RAS
CAS[0–3]
W
Data
Figure 15-4.
15-5