Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 141

Chapter 3
The MPC8xx Core
This chapter provides an overview of the MPC8xx core, summarizing topics described in further detail in
subsequent chapters in Part II. This chapter describes the functional specifications of the core. It is based
on the Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture,
which provides a more in-depth discussion of issues related to the 32-bit portion of the PowerPC
architecture implementation.
The subset of PowerPC instructions supported by the MPC885 is listed in Chapter 5, "MPC885 Instruction
Set."
3.1 The MPC885 Core as a PowerPC Implementation
The core implements all PowerPC user-level instructions defined for 32-bit implementations except
floating-point instructions (load/store and arithmetic). Likewise, it supports those registers defined by the
PowerPC architecture necessary for the supported instructions.
The MPC885 core adheres to portions of the PowerPC architecture definition for supervisor operations.
For example, it implements the PowerPC exception model (excluding inappropriate exceptions, such as
those that support floating-point operations). The architecture-defined memory management model has
been modified to suit the specific needs of the MPC885 core. Additional exceptions are defined (as
permitted by the architecture) to support address translation.
The PowerPC architecture defines features not supported on the MPC885 hardware. These features
include support for 64-bit addressing, multiprocessing, floating-point arithmetic, and some memory
management features.
The core also implements MPC885-specific development support features such as breakpoint and
watchpoint mechanisms, program-flow tracking data generation, and debug mode operation.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 3-1