Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 289

Chapter 10
System Interface Unit
The system interface unit (SIU) controls system startup, initialization and operation, protection, and the
external system bus. The system configuration and protection function controls the overall system and
provides various monitors and timers, including the bus monitor, software watchdog timer, periodic
interrupt timer (PIT), decrementer, and timebase. The clock synthesizer generates the clock signals for
other modules and external devices with which the SIU interfaces. The main system clock can be changed
dynamically; and the baud rate generators and serial ports work with a fixed frequency. For more
information, see Chapter 14, "Clocks and Power Control."
The external bus interface handles the transfer of information between internal buses and the memory or
peripherals in the external address space. The MPC885 is designed to allow external bus devices to request
and obtain system bus mastership.
controller module provides a glueless interface to many types of memory devices and peripherals; it
supports a maximum of eight memory banks, each with its own device and timing attributes. Memory
control services are provided to both internal and external masters. The MPC885 supports circuit board
test strategies through user-accessible test logic that is fully compliant with the IEEE 1149.1 standard
described in Chapter 54, "IEEE 1149.1 Test Access Port."
The PCMCIA host adapter module provides all control logic for a PCMCIA interface. This interface
complies fully with the PCMCIA standard, Release 2.1+ (PC Card -16). It can support PCMCIA socket
with a maximum of eight memory or I/O windows.
10.1 Features
The following is a list of the SIU's main features:
• System configuration and protection
• System interrupt configuration
• System reset monitoring and generation
• Clock synthesizer
• Power management
• Decrementer
• Time base
• Periodic interrupt timer (PIT)
• External bus interface control
• Eight memory banks supported by the memory controller
• Debug support
Freescale Semiconductor
Chapter 12, "External Signals,"
MPC885 PowerQUICC Family Reference Manual, Rev. 2
describes bus operation. The memory
10-1