Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 623

20.2.4.2 SI Mode Register (SIMODE)
The SI mode register (SIMODE), shown in
channels and SMCs.
0 1
Field SMC2 SMC2CS
Reset
R/W
Addr
16 17
Field SMC1 SMC1CS
Reset
R/W
Addr
This register is affected by HRESET and SRESET.
Bits Name
0, 16 SMC x SMC x connection
0 NMSI mode. The clock source is determined by SMC x CS and the data comes from a dedicated
pin (SMTXD1 and SMRXD1 for SMC1 or SMTXD2 and SMRXD2 for SMC2) in NMSI mode.
1 SMC x is connected to the multiplexed SI (TDM channel).
1–3, SMC x CS SMC x clock source (NMSI mode). SMC x can take its Tx and Rx clocks from a baud rate generator
17–19 or one of four pins from the bank of clocks. However, Tx and Rx clocks must be common when
connected to the NMSI.
000 BRG1
001 BRG2
010 BRG3
011 BRG4
100 CLK1 for SMC1; CLK5 for SMC2
101 CLK2 for SMC1; CLK6 for SMC2
110 CLK3 for SMC1; CLK7 for SMC2
111 CLK4 for SMC1; CLK8 for SMC2
4–5, SDM x SI diagnostic mode for TDMa/b. In modes 01,10, and 11, Rx and Tx clocks should be common.
20–21 00 Normal operation
01 Automatic echo. The TDM transmitter automatically resends its Rx data bit-by-bit. The Rx
10 Internal loopback. TDM transmitter output is connected internally to the TDM receiver
11 Loopback control. TDM transmitter output is connected internally to the TDM receiver
Freescale Semiconductor
Figure
3 4 5 6
SDMb RFSDb
19 20 21 22
SDMa RFSDa
Figure 20-13. SI Mode Register (SIMODE)
Table 20-5. SIMODE Field Descriptions
section operates normally, but the Tx section can only resend Rx data. L1GR x is ignored.
input—L1TXD x is connected to L1RXD x . The receiver and transmitter operate normally, but
data on L1RXD x is ignored. Data appears on L1TXD x , L1RQ x is asserted normally, and
L1GR x is ignored.
input—L1TXD x is connected to L1RXD x . Transmitter output L1TXD x and L1RQ x are inactive.
Provides loopback testing of the entire TDM without affecting the external serial lines.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
20-13, defines the SI operation modes for the TDM
7 8 9 10
DSCb CRTb STZb CEb
0
R/W
0xAE0
23 24 25 26
DSCa CRTa STZa CEa
0
R/W
0xAE2
Table 20-5 describes the SIMODE fields.
Description
Serial Interface
11 12 13 14 15
FEb GMb TFSDb
27 28 29 30 31
FEa GMa TFSDa
20-17