Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 769

SCC Ethernet Mode
of the CRC-encoded result to generate a number between 1 and 64. Bits 31–30 of the CRC result select
one of the GADDRs or IADDRs; bits 29–26 of the CRC result indicate the bit in that register.
When the ethernet controller receives a frame, the same process is used. If the CRC generator selects a bit
that is set in the group/individual hash table, the frame is accepted. Otherwise, it is rejected. So, if eight
group addresses are stored in the hash table and random group addresses are received, the hash table
prevents roughly 56/64 (87.5%) of the group address frames from reaching memory. Frames that reach
memory must be further filtered by the processor to determine if they contain one of the eight preferred
addresses.
Better performance is achieved by using the group and individual hash tables simultaneously. For instance,
if eight group and eight physical addresses are stored in their respective hash tables, 87.5% of all frames
are prevented from reaching memory. The effectiveness of the hash table declines as the number of
addresses increases. For instance, with 128 addresses stored in a 64-bin hash table, the vast majority of the
hash table bits are set, thus preventing a small fraction of the frames from reaching memory.
Hash tables cannot be used to reject frames that match a set of entered addresses because unintended
addresses are mapped to the same bit in the hash table.
27.12 Interpacket Gap Time
The receiver receives back-to-back frames with a minimum interpacket spacing of 9.6 µs. In addition, after
the backoff algorithm, the transmitter waits for carrier sense to be negated before resending the frame.
Retransmission begins 9.6 µs after carrier sense is negated if it stays negated for at least 6.4 µs.
27.13 Handling Collisions
If a collision occurs as a frame is being sent, the ethernet controller continues sending for at least 32 bit
times, thus sending a JAM pattern of 32 ones. If a collision occurs during the preamble sequence, the JAM
pattern is sent at the end of the sequence.
If a collision occurs within 64 byte times, the retry process is initiated. The transmitter waits a random
number of slot times (512 bit times or 52 µs). If a collision occurs after 64 byte times, no retransmission
is performed and the buffer is closed with an LC error indication. If a collision occurs while a frame is
being received, reception stops. This error is reported only in the BD if the length of the frame exceeds
MINFLR or if PSMR[RSH] = 1.
27.14 Internal and External Loopback
Both internal and external loopback are supported by the ethernet controller. In loopback mode, both of
the SCC FIFOs are used and the channel actually operates in a full-duplex fashion. Both internal and
external loopback are configured using combinations of PSMR[LPB] and GSMR[DIAG]. Because of the
full-duplex nature of the loopback operation, the performance of the other SCCs is degraded.
Internal loopback disconnects the SCC from the serial interface. Receive data is connected to the transmit
data and the receive clock is connected to the transmit clock. Data from the transmit FIFO is received
immediately into the receive FIFO. There is no heartbeat check in this mode; configure TENA as a
general-purpose output.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 27-13