Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 253

Page Size
1 Kbyte
4 Kbyte
16 Kbyte
512 Kbyte
8 Mbyte
The page size and the level-two base address are read from the level-one descriptor. If the page size is 512
Kbytes or 8Mbytes, the level-two base address is used directly as the address of the level-two descriptor.
If the page size is less than 512 Kbytes, the address of the level-two descriptor is determined by indexing
the level-two base address by EA[12–21]. For 4Kbyte or 16 Kbyte pages, this requires that multiple
identical level-two descriptors be provided. This is summarized in
The number of replaced bits depends on the page size, as shown in
address bits are taken directly from the effective address.
8.7.1 Level-One Descriptor
Table 8-3 describes the level-one descriptor format supported by the hardware to minimize the software
tablewalk routine.
Bits Name
0–19 L2BA Level-2 table base address. Bits 18–19 should be 0b00 unless MD_CTR[TWAM] = 1.
20–22 — Reserved
23–26 APG Access protection group
27 G Guarded memory attribute for entry
0 Nonguarded memory
1 Guarded memory
28–29 PS Page size level one. Used with the level-two (L2) descriptor's small-page-size (SPS) field; see
Section 8.7.3, "Page Size."
00 Small (4 Kbyte or 16 Kbyte)
01 512 Kbyte
10 Reserved
11 8 Mbyte
30 WT Writethrough attribute for entry
0 Copyback cache policy region (default)
1 Writethrough cache policy region
31 V Level-one segment valid bit
0 Segment is not valid
1 Segment is valid
Freescale Semiconductor
Table 8-2. Number of Replaced EA Bits per Page Size
Table 8-3. Level-One Segment Descriptor Format
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Number of Replaced EA Bits
20
20
18
13
9
Table 8-1.
Table 8-2. The remaining physical
Description
Memory Management Unit
8-11