Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 229

Instruction and Data Caches
The data cache performs the invalidate all command in one clock cycle.
7.3.2.2.6 Data Cache Flush Cache Block Command
The data cache flush cache block command (DC_CST[CMD] = 0b1110) is used to write the contents of
an unlocked, modified-valid cache block to memory and subsequently invalidate that cache block. If the
cache block is unmodified-valid, the cache block is invalidated without writing the contents to memory. If
the cache block is locked or if it is marked invalid, no operation is performed.
If a bus error occurs while executing the DC_CST flush cache block command, DC_CST[CCER1] is set
and a machine check exception is generated. The data of the cache block flagged by the bus error is
contained in the copyback buffer; it will have already been flushed from the data cache array. See
Section 7.3.2.1, "Reading Data Cache Tags and Copyback Buffer," for more information.
The cache control instructions dcbst and dcbf can also be used to flush the data cache. Note that the cache
control instructions operate on effective addresses that are translated while the DC_CST flush cache block
command operates on a physically addressed block contained within the data cache. When there is a need
to restrict the flushing to a specific memory area or to maintain architectural compliance, it is
recommended to use the cache control instructions; when there is a need to flush the entire data cache and
there is no concern for architectural compliance, using the DC_CST flush cache block command is more
efficient.
7.4 Cache Control Instructions
The PowerPC architecture defines instructions for controlling both the instruction and data caches. The
cache control instructions, icbi, dcbt, dcbtst, dcbz, dcbst, dcbf, and dcbi, are intended for the
management of the local caches. In the following descriptions, the memory/cache access attributes refer
to the write-through/write-back, caching-inhibited/caching-allowed, guarded/not guarded status of the
addressed page.
Note that the MPC885 does not broadcast cache control instructions nor does it snoop such broadcasts.
A TLB miss exception is generated if the effective address of one of these instructions cannot be translated
and data address relocation is enabled. A TLB error exception is generated if these instructions encounter
a TLB protection violation.
7.4.1 Instruction Cache Block Invalidate (icbi)
The effective address is computed, translated, and checked for protection violations as defined in the
PowerPC architecture. This instruction is treated as a store with respect to address translation and memory
protection. If the address hits an unlocked block in the instruction cache, the cache block is placed in the
invalid state. If the address misses in the instruction cache or if the block is locked, no action is taken. The
function of this instruction is independent of the memory/cache access attributes.
This command is not privileged and has no associated error cases. The instruction cache performs the icbi
instruction in one clock cycle. To accurately calculate the latency of this instruction, bus latency should be
taken into consideration.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 7-17