Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 820

Powerquicc family

Table of Contents

Serial Management Controllers (SMCs)

Handling Errors in the SMC Transparent Controller

The SMC uses BDs and the SMCE to report message transmit and receive errors.

The channel stops sending the buffer, closes it, sets UN in the BD, and generates a TXE interrupt if

it is enabled. The channel resumes sending after a

occur between frames.

The SMC maintains an internal FIFO for receiving data. If the buffer is in external memory, the CP

begins programming the SDMA channel when the first character is received into the FIFO. If a FIFO

overrun occurs, the SMC writes the received data character over the previously received character.

The previous character and its status bits are lost. Then the channel closes the buffer, sets OV in

the BD, and generates the RX interrupt if it is enabled. Reception continues as normal.

SMC Transparent Receive BD (RxBD)

Using BDs, the CP reports information about the received data for each buffer and closes the current

buffer, generates a maskable interrupt, and starts to receive data into the next buffer after one of the

following events:

An overrun error occurs.

A full receive buffer is detected.

ENTER HUNT MODE

Figure 29-13

shows the SMC transparent RxBD format.

describes SMC transparent RxBD fields.

0 The buffer is full or reception was aborted due to an error. The core can read or write any fields

of this RxBD. The CP does not use this BD while E = 0.

1 The buffer is empty or is receiving data. The CP owns this RxBD and its buffer. Once E is set, the

core should not write any fields of this RxBD.

Reserved, should be cleared.

Table 29-13. SMC Transparent Error Conditions

command is issued.

Figure 29-13. SMC Transparent Receive BD (RxBD)

Table 29-14. SMC Transparent RxBD Field Descriptions

MPC885 PowerQUICC Family Reference Manual, Rev. 2

Descriptions

RESTART TRANSMIT

Rx Buffer Pointer

command. Underrun cannot

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