Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 946

CPM Interrupt Controller
Communications Processor Module
(CPM)
Port C[4:15]
CPM Timer[1–4]
USB
SCC[2–4]
SMC[1–2]
SPI
I 2 C
PIP
IDMA[1–2]
SDMA
RISC Timers
Although all CPM interrupts are presented to the SIU at the same priority level (specified in CICR[IRL]),
individual CPM interrupt sources are prioritized as described in
Priorities." The MPC885 provides limited ability to reorder the interrupt priorities of SCCs and to specify
the highest priority interrupt source.
As shown in Figure 35-1, when the CIPR indicates that an unmasked interrupt source is pending, the CPIC
sends an interrupt request to the SIU at the interrupt level specified in CICR[IRL]. The CPIC then waits
for the interrupt to be recognized. The core honors the interrupt request and then acknowledges the
interrupt by setting the IACK bit in the CPM interrupt vector register (CIVR). When CIVR[IACK] is set,
the contents of CIVR[VN] are updated with the 5-bit vector corresponding to the sub-block with the
highest current priority. CIVR[IACK] is cleared after one clock cycle.
35.2 CPM Interrupt Source Priorities
The CPIC has 29 interrupt sources that assert a single programmable interrupt request level to the core.
Default interrupt priorities are as shown in
35-2
System Interface Unit (SIU)
IRQ[0:4]
IRQ[6:7]
Decrementer
Timebase
CPM
Periodic
Interrupt
Interrupt Timer
Controller
PCMCIA
Figure 35-1. MPC885 Interrupt Structure
Table
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Software
Watchdog Timer
Generator
IRQ0
Edge/
Level
Level 7
Level 6
Level 5
Level 4
SIU
Interrupt
Level 3
Controller
Level 2
Level 1
Level 0
Debug
Section 35.2, "CPM Interrupt Source
35-1.
NMI
System Reset
Interrupt
Decrementer
MPC8xx
Core
External
Interrupt
Debug
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