Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 597

Figure 19-8 shows the descriptor structure.
Offset
0 1
0x00 V —
0x02
0x04
0x06
0x08
0x0A
0x0C
0x0E
Table 19-7 describes an IDMA descriptor's status-and-control field.
Bits Name
0 V Valid. Ready for processing
0 Invalid. Not ready for transfer. The user can write to this descriptor and its buffer. When
buffer-chaining, the CP clears the V bit after the buffer has been transferred.
1 Valid for transfer. The user should not write to this descriptor or its buffer once the V bit is set.
Note: When an error condition is detected, the CP clears the V bit.
1 — Reserved
2 W Wrap. Marks the end of the BD table
0 Not the last descriptor in the BD table
1 Last descriptor in the BD table. After this descriptor has been processed, the CP wraps the
current BD pointer (IBPTR) back to the top of the BD table (IBASE).
3 I Interrupt. Enable the maskable auxiliary-done (AD) interrupt
0 IDSR[AD] is not flagged after this BD is processed.
1 IDSR[AD] is flagged after this BD is processed.
4 L Last. Marks the end of a buffer chain and enables the maskable DONE interrupt
0 Not the last BD of a buffer chain
1 Last BD of a buffer chain. When the transfer count is exhausted, IDSR[DONE] is flagged,
regardless of the I bit
5 — Reserved
6 CM Continuous mode. Selects buffer-chaining or auto-buffering; see
and Buffer-Chaining."
0 Normal mode (buffer-chaining). The CP clears the V bit after this descriptor is processed.
1 Continuous mode (auto-buffering). The CP does not clear the V bit after this descriptor is
processed.
7–15 — Reserved
Freescale Semiconductor
2 3 4 5 6
W I L — CM
DFCR
Source Buffer Pointer
Destination Buffer Pointer
Figure 19-8. IDMA Buffer Descriptor Structure
Table 19-7. IDMA BD Status and Control Bits
MPC885 PowerQUICC Family Reference Manual, Rev. 2
SDMA Channels and IDMA Emulation
7
Buffer Length
Description
Section 19.3.4.2, "Auto-Buffering
15
—
SFCR
19-11