Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 454

Memory Controller
15.4.4 Machine A Mode Register/Machine B Mode Registers
(M x MR)
The machine x mode register (MAMR and MBMR) contain the configuration for UPMA and UPMB,
respectively. See Figure
0
Field
Reset
R/W
Addr
16 17
Field G0CL x
Reset 000
R/W
Addr
Figure 15-10. Machine A Mode Register/Machine B Mode Register (M x MR)
This register is affected by HRESET but is not affected by SRESET.
MAMR/MBMR.
Bits Name
PT x
0–7
8 PT x E
9–11 AM x
12 —
15-14
15-1.
PT x
xxxx_xxxx_0000_0000
(IMMR & 0xFFFF0000) + 0x170
18 19 20
GPL x 4DIS RLF x
1 0000
(IMMR & 0xFFFF0000) + 0x172
Table 15-6. M x MR Field Descriptions
Periodic timer x period. Affects periodic timer x and determines the timer period service rate
according to the following equation, which determines value for UPM x to refresh memory:
System Clock (MHz)
PTx = -------------------------------------------------------------------------------------------------------------------- -
2 ×
[
SCCR DFBRG
2
NCS is an integer between 1 and 8 that represents the number of enabled chip selects that
are serviced by this UPM. SCCR[DFBRG] is defined in
Reset Control Register (SCCR)."
access or refresh must occur every 15.6 µs. Given a 25-MHz system clock with the required
service rate of 15.6µs, a periodic timer prescaler = 32, and DFBRG = 0, PT x = (25 x 15.6)
2 0
x
/ (2 x 32x 1) = 12.
Periodic timer x enable. Allows the periodic timer x to request service.
0 Periodic timer x is disabled.
1 Periodic timer x is enabled.
Address multiplex size x . When internal address multiplexing is used, this field specifies how
the address on the external bus is multiplexed, when enabled (see
bit enables address multiplexing in the first clock cycle. The AM x field of the RAM array entry
enables address multiplexing in subsequent clock cycles. (see
Reserved, should be cleared.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
7 8 9 10
PT x E AM x
R/W
23 24
WLF x
0000
R/W
Table 15-6
Description
×
Service Duration (µs)
]
× ×
Prescaler (PTP) NCS
Section 14.6.1, "System Clock and
For example, for DRAM to maintain data integrity, an
11 12 13 14 15
— DS x —
27 28 31
TLF x
0000
describes bits for
Table 15-18). The SAM
Table 15-19).
Freescale Semiconductor