Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 226

Instruction and Data Caches
Table 7-9 describes the bits of the DC_DAT register.
Bits Name
0–31 DAT Data cache command data. The data received when reading information from the data cache.
See
7.3.2.1 Reading Data Cache Tags and Copyback Buffer
The MPC885 supports reading the tags, the state bits and the lock bits stored in the data cache as well as
the last copyback address, and data words in the copyback buffer. The data cache read command, issued
by reading DC_DAT, uses the DC_ADR register to qualify what is to be read.
fields of the DC_ADR register during a data cache read command.
0–17
Reserved 0 Tags
1 Copyback buffer
To read the copyback buffer data or the tags stored in the data cache, do the following:
1. Write the address of the copyback buffer or tag to be read to the DC_ADR according to the format
shown in Table 7-10.
Note that it is also possible to read this register for debugging purposes.
2. Read the DC_DAT register. Note that writing to the DC_DAT register is illegal. A write to
DC_DAT results in an undefined data cache state.
For tag array (DC_ADR[18] = 0) read commands, the tag and state information is placed in the target
general-purpose register.
Table 7-11. DC_DAT Format for a Tag Read (DC_ADR[18] = 0)
0–19 20–21
Tag value Reserved
The last copyback address or data buffer can be read by using the copyback buffer read command
(DC_ADR[18] = 1). The copyback buffer select field (DC_ADR[20–27]), shown in
determines which word of the cache block in the copyback buffer is read.
7-14
Table 7-9. Data Cache Data Port Register—DC_DAT
Section 7.3.2.1, "Reading Data Cache Tags and Copyback Buffer,"
Table 7-10. DC_ADR Fields for Cache Read Commands
18
0 Way 0
1 Way 1
Reserved
Figure 7-11 provides the format of the DC_DAT register for a tag read.
22
0 Invalid 0 Unlocked
1 Valid 1 Locked
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
19 20–27
Set select
(0–255)
Copyback buffer address/
data-word select
23 24
LRU bit of this 0 Unmodified
set 1 Modified
for more information.
Table 7-10 describes the
28–31
Reserved
25 26–31
Reserved
Table 7-12,
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