Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 726

Powerquicc family

Table of Contents

SCC Asynchronous HDLC Mode and IrDA

Exceptions to RFC 1549

An unmapped control character that follows 0x7D is modified by the XOR process. The CRC

check should catch this.

In addition to the abort sequence, frames are terminated by the following errors:

— CD (carrier detect) lost

— Receiver overrun

— Framing error

— Break sequence

If an invalid sequence(0x7D7D) is received, the first control escape character is discarded, and the

second is unconditionally XORed with 0x20. The sequence is thus stored in the buffer as 0x5D.

Asynchronous HDLC Channel Implementation

The following points are specific to asynchronous HDLC channel implementation:

Flag sequence—The transmitter automatically generates the opening and closing flags. The

receiver removes opening and closing flags before writing a frame to memory and receives frames

with only one shared flag between frames, ignoring multiple flags.

Address field—The address field is neither generated nor examined by the microcode while

sending or receiving. The destination address field of the frame must be included in the Tx buffer.

Any address field compression, expansion, or checking must be performed by the core.

Control field—The control field is neither generated nor examined by the microcode during a

transfer. The control field of the frame must be included in the buffer. Any control field

compression, expansion, or checking is done by the core.

Frame check sequence—When sending, the frame check sequence (FCS) is appended to the frame

before the closing flag is sent. The FCS is generated on the original frame before transparency

characters, start/stop bits, or flags are added. When receiving, the FCS is checked automatically

and calculated after any transparency characters, start/stop bits, and flags are removed. For both,

the controller uses only a 16-bit CRC-CCITT polynomial.

Encoding—The asynchronous HDLC controller supports 8 data bits, one start bit, one stop bit, and

no parity. Program PSMR[CHLN] to 0b11 for proper operation.

Idle characters—When sending, the asynchronous HDLC controller sends idle characters when no

data is available; when receiving, it ignores idle characters.

MPC885 PowerQUICC Family Reference Manual, Rev. 2

Freescale Semiconductor