Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 883

Chapter 32
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I C Controller
The inter-integrated circuit (I
as microcontrollers, EEPROMs, real-time clock devices, A/D converters, and LCD displays. The I
controller uses a synchronous, multimaster bus that can connect several integrated circuits on a board. It
uses two signals—serial data (SDA) and serial clock (SCL)—to carry information between the integrated
circuits connected to it.
As shown in Figure 32-1, the I
baud-rate generator (BRG), and a control unit. The transmit and receive sections use the same clock, which
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is derived from the I C BRG when in master mode and generated externally when in slave mode. Wait
states are inserted during a data transfer if SCL is held low by a slave device. In the middle of a data
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transfer, the master I C controller recognizes the need for wait states by monitoring SCL. However, the
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I C controller has no automatic time-out mechanism if the slave device does not release SCL; therefore,
software should monitor how long SCL stays low to generate bus timeouts.
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The I C receiver and transmitter are double-buffered, which corresponds to an effective two-character
FIFO latency. In normal operation, the msb (bit 0) is shifted out first. When the I
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I C mode register (I2MOD[EN] = 0), it consumes little power.
Freescale Semiconductor
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C ) controller lets the MPC885 exchange data with other I
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C controller consists of transmit and receive sections, an independent
Peripheral Bus
Rx Data Register Tx Data Register
Shift Register Shift Register
Control
Baud-Rate Generator
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Figure 32-1. I C Controller Block Diagram
MPC885 PowerQUICC Family Reference Manual, Rev. 2
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C devices, such
U Bus
Mode Register
SDA
SCL
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C is not enabled in the
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C
32-1