Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 204

Exceptions
6.1.3 Implementation-Specific Exceptions
The following sections describe the MPC885's implementation-specific exceptions.
6.1.3.1 Software Emulation Exception (0x01000)
A software emulation exception occurs as a result of one of the following conditions:
• When executing any unimplemented instruction, including all illegal and unimplemented optional
and floating-point instructions.
• When executing a mtspr or mfspr that specifies an on-core unimplemented register, regardless of
SPR[0].
• When executing a mtspr or mfspr that specifies an off-core unimplemented register and SPR[0]
= 0 or MSR[PR] = 0 (no program exception condition).
In addition, Table 6-12 shows the following set of registers:
Table 6-12. Register Settings after a Software Emulation Exception
Register
SRR0 Set to the EA of the instruction that caused the exception.
SRR1 1–4 0
10–15 0
Others Loaded from MSR[16-31]. SRR1[30] is cleared only by loading a zero from MSR[RI].
MSR IP No change
ME No change
LE Copied from the ILE setting of the interrupted process
Other 0
Execution resumes at offset 0x01000 from the base address indicated by MSR[IP].
6.1.3.2 Instruction TLB Miss Exception (0x01100)
This type of exception occurs if MSR[IR] = 1 and an attempt is made to fetch an instruction from a page
whose effective page number cannot be translated by TLB. As shown in
are set:
6-12
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Setting
Table 6-13, the following registers
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