Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 750

SCC BISYNC Mode
Table 26-11 describes SCC BISYNC RxBD status and control fields.
Table 26-11. SCC BISYNC RxBD Status and Control Field Descriptions
Bits Name
0 E Empty
0 The buffer is full or stopped receiving because of an error. The core can read or write any fields
of this RxBD. The CP does not use this BD as long as the E bit is zero.
1 The buffer is not full. The CP controls this BD and buffer. The core should not update this BD.
1 — Reserved, should be cleared.
2 W Wrap (last BD in table)
0 Not the last BD in the table.
1 Last BD in the table. After this buffer is used, the CP receives incoming data into the first BD that
RBASE points to. The number of BDs in this table is determined by the W bit.
3 I Interrupt
0 No interrupt is generated after this buffer is used.
1 SCCE[RXB] is set when the controller closes this buffer, which can cause an interrupt if it is
enabled.
4 L Last in frame. Set when this buffer is the last in a frame. If CD is negated in envelope mode or an
error is received, one or more of the OV, CD, and DE bits are set. The controller writes the number
of frame octets to the data length field.
0 Not the first buffer in the frame.
1 The first buffer in the frame.
5 F First in frame. Set when this is the first buffer in a frame.
0 Not the first buffer in a frame.
1 First buffer in a frame
6 CM Continuous mode
0 Normal operation.
1 The CP does not clear E after this BD is closed; the buffer is overwritten when the CP accesses
this BD next. However, E is cleared if an error occurs during reception, regardless of how CM is
set.
7 — Reserved, should be cleared.
8 DE DPLL error. Set when a DPLL error occurs during reception. In decoding modes where a transition
is should occur every bit, the DPLL error is set when a transition is missing.
9–10 — Reserved, should be cleared.
11 NO Rx non-octet-aligned frame. Set when a frame is received containing a number of bits not evenly
divisible by eight.
12 PR Parity error. Set when a character with parity error is received. Upon a parity error, the buffer is
closed; thus, the corrupted character is the last byte of the buffer. A new Rx buffer receives
subsequent data.
13 CR Rx CRC error. Set when this frame contains a CRC error. Received CRC bytes are always written
to the receive buffer.
14 OV Overrun. Set when a receiver overrun occurs during frame reception.
15 CD Carrier detect lost. Indicates when the carrier detect signal, CD, is negated during frame reception.
26-12
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Freescale Semiconductor