Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 760

SCC Ethernet Mode
— Number of collisions exceeded the maximum allowed
— Number of retries per frame
— Deferred frame indication
— Late collision
• Receiver network management and diagnostics
— CRC error indication
— Nonoctet alignment error
— Frame too short
— Frame too long
— Overrun
— Busy (out of buffers)
• Error counters
— Discarded frames (out of buffers or overrun occurred)
— CRC errors
— Alignment errors
• Internal and external loopback mode
27.3 Learning Ethernet on the MPC885
The standard SCC functionality has been enhanced to support ethernet. First-time MPC885 users who plan
to use ethernet should first read the following:
• Chapter 21, "Serial Communications Controllers,"
• Chapter 17, "Communications Processor Module and CPM Timers,"
issues special commands to the ethernet channel. The dual-port RAM loads ethernet parameters
and initializes BDs for the ethernet channel to use.
• Chapter 19, "SDMA Channels and IDMA Emulation,"
transfer data between the ethernet channel and system memory.
• Section 20.3, "NMSI Configuration,"
of clocks.
• Chapter 27, "SCC Ethernet Mode,"
• Chapter 34, "Parallel I/O Ports,"
active.
• Chapter 35, "CPM Interrupt Controller,"
generated to the core.
27-4
explains how clocks are routed to the SCCs through the bank
should be read next.
shows how to configure the preferred ethernet pin functions to be
defines SCC interrupt priorities and how interrupts are
MPC885 PowerQUICC Family Reference Manual, Rev. 2
describes basic operation of the SCCs.
describes how the CPM
discusses how SDMA channels are used to
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