Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 128

Memory Map
Table 2-1. MPC885 Internal Memory Map (IMMR[14–15]=00) (continued)
Offset
A68 PSMR4—SCC4 protocol specific mode register
A6A–A6B Reserved
A6C TODR4—SCC4 transmit on demand register
A6E DSR4—SCC4 data synchronization register
A70 SCCE4—SCC4 event register
A72–A73 Reserved
A74 SCCM4—SCC4 mask register
A76 Reserved
A77 SCCS4—SCC4 status register
A78–A81 Reserved
A82 SMCMR1—SMC1 mode register
A84–A85 Reserved
A86 SMCE1—SMC1 event register
A87–A89 Reserved
A8A SMCM1—SMC1 mask register
A8B–A91 Reserved
A92 SMCMR2—SMC2 mode register
A94–A95 Reserved
A96 SMCE2—SMC2 event register
A97–A99 Reserved
2-10
Name
Serial Management Controller 1 (SMC1)
Serial Management Controller 2 (SMC2)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Size Section/Page
16 bits 21.2.2/21-10
22.16/22-13
25.13.1/25-8 (Asynchronous HDLC)
26.11/26-10
27.17/27-15
28.8/28-7 (Transparent)
2 bytes —
16 bits 21.2.4/21-10
16 bits 21.2.3/21-10
16 bits 22.20/22-22
23.12/23-14
2 bytes
25.13/25-8 (Asynchronous HDLC)
26.15/26-15
16 bits
28.12/28-11
1 byte —
8 bits 22.20/22-22
23.12/23-14
26.15/26-15
28.12/28-11
10 bytes —
16 bits 29.2.1/29-2
2 bytes —
8 bits 29.3.12/29-18
29.4.11/29-29
29.5.9/29-35
3 bytes —
8 bits 29.3.12/29-18
29.4.11/29-29
29.5.9/29-35
7 bytes —
16 bits 29.2.1/29-2
2 bytes —
8 bits 29.3.12/29-18
29.4.11/29-29
29.5.9/29-35
3 bytes —
Freescale Semiconductor
(UART)
(BISYNC)
(Ethernet)
(UART)
(HDLC)
(BiSYNC)
(Transparent)
(UART)
(HDLC)
(BiSYNC)
(Transparent)
(UART)
(Transparent)
(GCI)
(UART)
(Transparent)
(GCI)
(UART)
(Transparent)
(GCI)