Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 52

Figure
Number
13-20 Interface to Different Port Size Devices ............................................................................. 13-24
13-21 Basic Bus Arbitration Protocol ........................................................................................... 13-26
13-22 Bus Busy (BB) and Transfer Start (TS) Connection Example............................................ 13-27
13-23 Bus Arbitration Timing Diagram ........................................................................................ 13-28
13-24 Internal Bus Arbitration State Machine .............................................................................. 13-29
13-25 Termination Signals Protocol Basic Connection................................................................. 13-34
13-26 Termination Signals Protocol Timing Diagram .................................................................. 13-34
13-27 Reservation On Local Bus .................................................................................................. 13-36
13-28 Reservation on Multilevel Bus Hierarchy........................................................................... 13-37
13-29 Retry Transfer Timing–Internal Arbiter.............................................................................. 13-38
13-30 Retry Transfer Timing–External Arbiter............................................................................. 13-39
13-31 Retry on Burst Cycle........................................................................................................... 13-40
14-1 Clock Source and Distribution.............................................................................................. 14-2
14-2 Clock Module Components .................................................................................................. 14-3
14-3 Crystal Circuit Examples ...................................................................................................... 14-8
14-4 Clock Dividers ...................................................................................................................... 14-9
14-5 Frequency Dividers for GCLKx.......................................................................................... 14-10
14-6 Divided System Clocks (GCLKx) Timing Diagram ........................................................... 14-11
14-7 Memory Controller and External Bus Clocks Timing
Diagram for EBDF=0 and EBDF=1 .............................................................................. 14-11
14-8 Memory Controller and External Bus Clocks Timing
Diagram for (CSRC=0 and DFNH=1) or (CSRC=1 and DFNL=0) .............................. 14-12
14-9 BRGCLK Divider ............................................................................................................... 14-13
14-10 SYNCCLK Divider............................................................................................................. 14-14
14-11 MPC885 Power Rails.......................................................................................................... 14-15
14-12 System Clock and Reset Control Register (SCCR) ............................................................ 14-18
14-13 PLL and Reset Control Register (PLPRCR)....................................................................... 14-21
15-1 Memory Controller Block Diagram ..................................................................................... 15-3
15-2 Memory Controller Machine Selection................................................................................. 15-4
15-3 Simple System Configuration ............................................................................................... 15-5
15-4 Basic Memory Controller Operation..................................................................................... 15-6
15-5 Base Registers (BRx) ............................................................................................................ 15-9
15-6 BR0 Reset Defaults ............................................................................................................... 15-9
15-7 Option Registers (ORx) ...................................................................................................... 15-11
15-8 OR0 Reset Defaults............................................................................................................. 15-11
15-9 Memory Status Register (MSTAT) ..................................................................................... 15-13
15-10 Machine A Mode Register/Machine B Mode Register (MxMR) ....................................... 15-14
15-11 Memory Command Register (MCR) .................................................................................. 15-16
15-12 Memory Data Register (MDR) ........................................................................................... 15-17
15-13 Memory Address Register (MAR)...................................................................................... 15-17
15-14 Memory Periodic Timer Prescaler Register (MPTPR) ....................................................... 15-18
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Figures
Title
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Page
Number
Freescale Semiconductor