Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 429

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CLKOUT Special Considerations: 1:2:1 Mode

To enable synchronization of a system to the EXTCLK signal while still allowing the internal circuits of

the MPC885 to operate at an increased frequency, it is necessary to maintain synchronization of the

EXTCLK and CLKOUT signal. Specifically, this operation entails:

input clock source EXTCLK

internal clock of 2xEXTCLK, provided by multiplying EXTCLK by 2 in the DPLL (by

programming PLPRCR[MFI]=10, PLPRCR[MFN]=0, PLPRCR [MFD]=0, PLPRCR[PDF]=4,

PLPRCR[S]=0)

external bus clock CLKOUT with frequency equivalent to EXTCLK, provided by dividing

GCLK2 by 2 (by programming SCCR[EBDF]=01)

This is also known as 1:2:1 mode. In this mode, in order to allow multiple devices clocked by the same

EXTCLK source to maintain synchronization on the external bus, EXTCLK and CLKOUT must be in

phase. This operation can be guaranteed, but it requires that SCCR[EBDF] be written first, followed by

the write to PLPRCR[MFI, MFN, MFD]. Synchronization between EXTCLK and CLKOUT is only

possible when the total multiplication factor between EXTCLK and CLKOUT is maintained as an integer

Baud Rate Generator Clock (BRGCLK)

The baud rate generator clock (BRGCLK) is used by the four baud rate generators of the communication

processor module and by the memory controller refresh counter. The baud rate generator clock is

controlled independently in order to allow the baud rate generators and memory refresh rate to continue

operating at a fixed frequency, even when the rest of the MPC885 is operating at a reduced frequency.

BRGCLK defaults to divout1, where divout1 is equivalent to JDBCK divide by 2, but can be reduced in

frequency by a frequency divider. This frequency divider is controlled by SCCR[DFBRG].

The baud rate generator clock frequency is:

Synchronization Clock (SYNCCLK, SYNCCLKS)

The synchronization clock signals (SYNCCLK and SYNCCLKS, collectively as SYNCCLK) are used by

the signal synchronization circuitry in the serial ports of the communication processor module. The signal

synchronization circuitry is used to sample and synchronize asynchronous external signals provided to

these ports. SYNCCLK allows the serial interface, serial communication controller, and serial

Freescale Semiconductor

Figure 14-9. BRGCLK Divider

MPC885 PowerQUICC Family Reference Manual, Rev. 2

divout1 freq

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