Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 797

Powerquicc family

Table of Contents

These registers are affected by HRESET and SRESET.

Reserved, should be cleared

CLEN Character length (UART). Number of bits in the character minus one. The total is the sum of 1 (start

bit always present) + number of data bits (5–14) + number of parity bits (0 or 1) + number of stop

bits (1 or 2). For example, for 8 data bits, no parity, and 1 stop bit, the total number of bits in the

character is 1 + 8 + 0 + 1 = 10. So, CLEN should be programmed to 9.

Characters range from 5–14 bits. If the data bit length is less than 8, the msbs of each byte in

memory are not used on transmit and are written with zeros on receive. If the length is more than 8,

the msbs of each 16-bit word are not used on transmit and are written with zeros on receive.

The character must not exceed 16 bits. For a 14-bit data length, set SL to one stop bit and disable

parity. For a 13-bit data length with parity enabled, set SL to one stop bit. Writing values 0 to 3 to

CLEN causes erratic behavior.

Character length (transparent). The values 3–15 specify 4–16 bits per character. If a character is

less than 8 bits, the msbs of the byte in buffer memory are not used on transmit and are written with

zeros on receive. If character length is more than 8 bits but less than 16, the msbs of the half-word

in buffer memory are not used on transmit and are written with zeros on receive.

Note: Using values 0–2 causes erratic behavior. Larger character lengths increase an SMC

channel's potential performance and lowers the performance impact of other channels. For

instance, using 16- rather than 8-bit characters is encouraged if 16-bit characters are acceptable in

the end application.

Character length (GCI). Number of bits in the C/I and monitor channels of the SCIT channels 0 or

1. Values 0–15 correspond to 1–16 bits. CLEN should be 13 for SCIT channel 0 or GCI (8 data bits,

plus A and E bits, plus 4 C/I bits = 14 bits). It should be 15 for the SCIT channel 1 (8 data, bits, plus

A and E bits, plus 6 C/I bits = 16 bits).

Stop length. (UART)

0 One stop bit.

1 Two stop bits.

Reserved, should be cleared (transparent)

Monitor enable. (GCI)

0 The SMC does not support the monitor channel.

1 The SMC supports the monitor channel.

Freescale Semiconductor

0xA82 (SMCMR1), 0xA92 (SMCMR2)

Figure 29-2. SMC Mode Registers (SMCMR n )

Table 29-1. SMCMR Field Descriptions

MPC885 PowerQUICC Family Reference Manual, Rev. 2

Serial Management Controllers (SMCs)

describes SMCMR fields.