Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 171

Powerquicc family

Table of Contents

MPC885 Instruction Set

This chapter describes the instructions implemented by the MPC885. These instructions are organized by

the level of architecture in which they are implemented—UISA, VEA, and OEA. These levels are

described in

Section 3.2.1, "Levels of the PowerPC Architecture."

Operand Conventions

This section describes the operand conventions as they are represented in two levels of the architecture. It

also provides detailed descriptions of conventions used for storing values in registers and memory,

accessing the MPC885's registers, and representing data in these registers.

Data Organization in Memory and Data Transfers

Bytes in memory are numbered consecutively starting with 0. Each number is the address of the

corresponding byte.

Memory operands may be bytes, half words, words, or double words, or, for the load/store multiple and

move assist instructions, a sequence of bytes or words. The address of a memory operand is the address of

its first byte (that is, of its lowest-numbered byte).

Aligned and Misaligned Accesses

The operand of a single-register memory access instruction has a natural alignment boundary equal to the

operand length. In other words, the natural address of an operand is an integer multiple of the operand

length. A memory operand is said to be aligned if it is aligned at its natural boundary; otherwise it is

Operands for single-register memory access instructions have the characteristics shown in

(Although not permitted as memory operands, quad words are shown because quad-word alignment is

desirable for certain memory operands.)

Note: An "x" in an address bit position indicates that the bit can be 0 or 1 independent of the state of other bits in the address.

Freescale Semiconductor

Table 5-1. Memory Operands

MPC885 PowerQUICC Family Reference Manual, Rev. 2

Addr[28–31] if Aligned