Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 361

Table 12-2. MPC875/MPC870 Signal Descriptions (continued)
Hard
Name
Reset
HRESET Low
SRESET Low
XTAL Analog
driving
EXTAL Hi-Z
2
CLKOUT Note
EXTCLK Hi-Z
TEXP High
ALE_A Low
CE1_A High
CE2_A High
WAIT_A Hi-Z
IP_A0 Hi-Z
IP_A1 Hi-Z
IP_A2 Hi-Z
IOIS16_A
IP_A3 Hi-Z
Freescale Semiconductor
Number Type
E7 Open-drain Hard Reset—Asserting this open drain signal puts the MPC875 in
hard reset state.
C4 Open-drain Soft Reset—Asserting this open drain line puts the MPC875 in
soft reset state.
D6 Analog This output is one of the connections to an external crystal for the
Output internal oscillator circuitry.
D7 Analog Input This line is one of the connections to an external crystal for the
(3.3 V only) internal oscillator circuitry.
G4 Output Clock Out—This output is the clock system frequency.
B4 Input (3.3 V External Clock—This input is the external input clock from an
only) external source.
B3 Output Timer Expired—This output reflects the status of
PLPRCR[TEXPS].
B7 Output Address Latch Enable A—This output line is asserted when
MPC875 initiates an access to a region under the control of the
PCMCIA interface to socket A.
C15 Output Card Enable 1 Slot A—This output signal enables even byte
transfers when accesses to PCMCIA slot A are handled under the
control of the PCMCIA interface.
D14 Output Card Enable 2 Slot A—This output signal enables odd byte
transfers when accesses to PCMCIA slot A are handled under the
control of the PCMCIA interface.
D4 Input Wait Slot A—This input signal, if asserted low, causes a delay in
the completion of a transaction on the PCMCIA controlled Slot A.
G6 Input Input Port A 0—This input signal is monitored by the MPC875 and
its value is reflected in the PIPR and PSCR of the PCMCIA
interface.
F5 Input Input Port A 1—This input signal is monitored by the MPC875 and
its value is reflected in the PIPR and PSCR of the PCMCIA
interface.
D3 Input Input Port A 2—This input signal is monitored by the MPC875 and
its value and changes are reported in the PIPR and PSCR of the
PCMCIA interface.
I/O Device A is 16 Bits Ports Size—This input signal is monitored
by the MPC875 when a transaction under the control of the
PCMCIA interface is initiated to an I/O region in socket A of the
PCMCIA space.
E4 Input Input Port A 3—This input signal is monitored by the MPC875 and
its value is reflected in the PIPR and PSCR of the PCMCIA
interface.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
External Signals
Description
12-31