Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 325

Table 11-3. Hard Reset Configuration Word Field Descriptions (continued)
Bits Name
2 BBE Boot Burst Enable
0 The boot device does not support bursting.
1 The boot device does support bursting.
3 BDIS Boot disable. If BDIS is set, memory bank 0 is invalid; that is, BR0[V] is cleared. (See
"Base Registers
0 The memory controller is activated after reset so that it matches all addresses.
1 The memory controller is cleared after reset but is not activated.
4–5 BPS Boot port size. Defines the port size of the boot device as shown in the following chart.
00 32-bit port size.
01 8-bit port size.
10 16-bit port size.
11 Reserved.
6 — Reserved for future use and should be allowed to float.
7–8 ISB Initial internal space base select. Defines the initial value of the IMMR bits 0-15 and determines the
base address of the internal memory space.
00 0x00000000.
01 0x00F00000.
10 0xFF000000.
11 0xFFF00000.
9–10 DBGC Debug pin configuration. Selects the signal function of the following pins:
IP_B[0–1]/IWP[0–1]/VFLS[0–1] IP_B[0–1]
IP_B3/IWP2/VF2
IP_B4/LWP0/VF0
IP_B5/LWP1/VF1
OP2/MODCK1/STS
ALE_B/DSCK/AT1
IP_B2/IOIS16_B/AT2
IP_B6/DSDI/AT0
IP_B7/PTR/AT3
OP3/MODCK2/DSDO
Freescale Semiconductor
(BRx).")
Pin DBGC = 00
IP_B3
IP_B4
IP_B5
OP2
ALE_B
IP_B2
IP_B6
IP_B7
OP3
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
DBGC = 01 DBGC = 10
IWP[0–1] Reserved
IWP2
LWP0
LWP1
STS
AT1
AT2
AT0
AT3
OP3
Reset
Section 15.4.1,
DBGC = 11
VFLS[0–1]
VF2
VF0
VF1
STS
AT1
AT2
AT0
AT3
OP3
11-9