Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 54

Figure
Number
15-54 Single-Beat Read Access to Page-Mode DRAM................................................................ 15-65
15-55 Single-Beat Write Access to Page Mode DRAM ............................................................... 15-66
15-56 Burst Read Access to Page-Mode DRAM (No LOOP) ...................................................... 15-67
15-57 Burst Read Access to Page-Mode DRAM (LOOP)............................................................ 15-68
15-58 Burst Write Access to Page-Mode DRAM (No LOOP) ..................................................... 15-69
15-59 Burst Write Access to Page-Mode DRAM (LOOP) ........................................................... 15-70
15-60 Refresh Cycle (CAS before RAS) to Page-Mode DRAM .................................................. 15-71
15-61 Exception Cycle .................................................................................................................. 15-72
15-62 Optimized DRAM Burst Read Access................................................................................ 15-73
15-63 EDO DRAM Interface Connection..................................................................................... 15-74
15-64 EDO DRAM Single-Beat Read Access .............................................................................. 15-76
15-65 EDO DRAM Single-Beat Write Access ............................................................................. 15-77
15-66 EDO DRAM Burst Read Access ........................................................................................ 15-78
15-67 EDO DRAM Burst Write Access........................................................................................ 15-79
15-68 EDO DRAM Refresh Cycle (CAS before RAS) ................................................................ 15-80
15-69 EDO DRAM Exception Cycle............................................................................................ 15-81
15-70 Blank Work Sheet for a UPM ............................................................................................. 15-82
16-1 System with Two PCMCIA Sockets ..................................................................................... 16-2
16-2 Internal DMA Request Logic................................................................................................ 16-8
16-3 PCMCIA Interface Input Pins Register (PIPR) .................................................................... 16-9
16-4 PCMCIA Interface Status Changed Register (PSCR) ........................................................ 16-10
16-5 PCMCIA Interface Enable Register (PER)......................................................................... 16-11
16-6 PCMCIA Interface General Control Register (PGCRx)..................................................... 16-13
16-7 PCMCIA Base Register (PBR) ........................................................................................... 16-14
16-8 PCMCIA Option Register 0–7 (POR0–POR7)................................................................... 16-14
16-9 PCMCIA Single-Beat Read Cycle PRS = 0 PSST = 1 PSL = 3 PSHT = 1 ........................ 16-17
16-10 PCMCIA Single-Beat Read Cycle PRS = 0 PSST = 2 PSL = 4 PSHT = 1 ........................ 16-18
16-11 PCMCIA Single-Beat Read Cycle PRS = 0 PSST = 1 PSL = 3 PSHT = 0 ........................ 16-19
16-12 PCMCIA Single-Beat Write Cycle PRS = 2 PSST = 1 PSL = 3 PSHT = 1 ....................... 16-20
16-13 PCMCIA Single-Beat Write Cycle PRS = 3 PSST = 1 PSL = 4 PSHT = 3 ....................... 16-21
16-14 PCMCIA Single-Beat Write with Wait PRS = 3 PSST = 1 PSL = 3 PSHT = 0 ................. 16-22
16-15 PCMCIA Single-Beat Read with Wait PRS = 3 PSST = 1 PSL = 3 PSHT = 1.................. 16-23
16-16 PCMCIA I/O Read PPS = 1 PRS = 3 PSST = 1 PSL = 2 PSHT = 0 ................................. 16-24
16-17 PCMCIA I/O Read PPS = 1 PRS = 3 PSST = 1 PSL = 2 PSHT = 0 .................................. 16-25
16-18 PCMCIA DMA Read Cycle PRS = 4 PSST = 1 PSL = 3 PSHT = 0.................................. 16-26
17-1 CPM Block Diagram............................................................................................................. 17-2
17-2 MPC885 Application Design Example................................................................................. 17-4
17-3 CPM Timer Block Diagram .................................................................................................. 17-5
17-4 Timer Cascaded Mode Block Diagram................................................................................. 17-7
17-5 Timer Global Configuration Register (TGCR) ..................................................................... 17-8
17-6 Timer Mode Registers (TMR1–TMR4)................................................................................ 17-9
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Title
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Page
Number
Freescale Semiconductor