Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 905

Bits Name
7 EBSY Enable BUSY. The bit definition depends on whether T/R is set to receive or transmit. BUSY is not
affected by MODL programming if EBSY = 1.
T/R = 0 (Receiving):
0 Disable BUSY signal generation on PB31 for the receiver.
1 Enable the BUSY output on PB31. EBSY takes effect only if BUSY is configured as a PIP output
(PBPAR[31] = 0 and PBDIR[31] = 1).
T/R = 1 (Transmitting):
0 Ignore the BUSY input on PB31 for the transmitter.
1 Assertion of STB requires negation of BUSY. STB is not asserted until BUSY, input on PB31, is
negated. EBSY takes effect only if BUSY is configured as a PIP input (PBPAR[31] = PBDIR[31]
= 0).
8–9 TMOD Timing mode. Used to implement a Centronics-type receiver. Valid only when T/R = 0 (Rx operation)
and MODH = 11 (pulsed handshake). For the definition of these timing modes, see
"Pulsed Handshake Timing."
00 PIP receiver timing mode 0.
01 PIP receiver timing mode 1.
10 PIP receiver timing mode 2.
11 PIP receiver timing mode 3.
10–11 MODL Mode low. Determines the mode of the PIP's lower 8 signals, PB[24–31], which extend the PIP
interface to 16 bits. (If the PIP is 8-bit, program MODL to 0b00.)
00 Port B general-purpose I/O
01 Transparent transfer mode—controlled by the CP.
1x Mode of operation is controlled by MODH.
Note that BUSY is not affected by MODL programming if EBSY = 1.
12–13 MODH Mode high. Determines the mode of the PIP upper 10 signals, PB[14–23], which comprise the 8-bit
PIP and its control signals. Can be modified when the CP is not transferring data.
00 Port B general-purpose I/O (PIP disabled)
01 Transparent transfer mode—controlled by the CP.
10 Interlocked handshake mode—controlled by the CP or core.
11 Pulsed handshake mode—controlled CP or core.
14 HSC Host control
0 The CP controls transfers using PIP parameter RAM, buffer descriptors, and SDMA channels.
1 PIP data transfers are controlled by the core.
15 T/R Transmit/receive. Selects transmitter or receiver operation for the PIP.
0 Receive. Data is input to the PIP.
1 Transmit. Data is output from the PIP.
33.4.2 PIP Event Register (PIPE)
The PIP event (PIPE) register is used to generate interrupts and report events recognized by the PIP
controller. It shares the same address as the SMC2 event register, which cannot be used at the same time
as the PIP. Since PIP is not full duplex, the one PIPE register can report both transmit and receive events
concurrently.
When the PIP recognizes an event, it sets the corresponding event bit in the PIPE. PIPE interrupts can be
masked in the PIP mask register (PIPM). Writing ones to the PIPE bits clears the events; writing zeros has
no effect. All unmasked flags must be cleared before the CP clears internal interrupt requests.
shows the register format.
Freescale Semiconductor
Table 33-6. PIPC Field Descriptions (continued)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Parallel Interface Port (PIP)
Section 33.7.2.2,
Figure 33-6
33-9