Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 935

Bits Name
12–13 Reserved, should be cleared.
—
14–15 DREQ x Enable DMA request to the CPM. Set DREQ x only if IDMA is being used. Note that the IDMA
0 PC x is a general-purpose interrupt I/O signal. If PCDIR configures this signal as an input, the
1 As well as being a general-purpose interrupt signal PC x becomes an external request to the
34.4.1.5 Port C Interrupt Control Register (PCINT)
Each bit of the port C interrupt control (PCINT) register, shown in
signal to determine whether that line asserts an interrupt request on a high-to-low transition or on any
transition. PCINT is cleared by reset.
0
Field —
Reset
R/W
Addr
This register is affected by HRESET but is not affected by SRESET.
Bits Name
0–3 — Reserved, should be cleared.
4–15 EDM n Edge detect mode. The corresponding port C signal asserts an interrupt request.
0 Any edge on PC x generates an interrupt request.
1 A falling edge on PC x generates an interrupt request.
34.5 Port D
Port D signals are configured as follows in the port D pin assignment register (PDPAR):
• General-purpose I/O signal (the corresponding PDPAR[DDn] = 0)
• Dedicated on-chip peripheral signal (PDPAR[DDn] = 1)
PDPAR and the port D data direction register (PDDIR) are cleared at reset, thus configuring all port D
signals as general-purpose input signals.
Freescale Semiconductor
Table 34-16. PCSO Bit Descriptions (continued)
request function and the general-purpose interrupt function operate concurrently and
independently.
signal can generate an interrupt to the core, as controlled by the PCINT bits.
CPM for IDMA service. RCCR[DR x M] controls whether IDMA requests are edge- or
level-sensitive. The corresponding PCINT bits still control when a general-purpose interrupt
is generated.
3 4
Figure 34-15. Port C Interrupt Control Register (PCINT)
Table 34-17. PCINT Bit Descriptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Figure 34-15, corresponds to a port C
EDM4–EDM15
0
R/W
0x968
Table 34-17
Description
Parallel I/O Ports
15
describes PCINT bits.
34-17