Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 270

Memory Management Unit
Bits Name
24–26 PS Page size. (Values not shown are reserved)
000 4 Kbyte
001 16 Kbyte
011 512 Kbyte
111 8 Mbyte
27 SH Shared page
0 This entry matches only if the ASID field in the DTLB entry matches the value in M_CASID
1 ASID comparison is disabled for the entry
28–31 ASID Address space ID of the DTLB entry to be compared with M_CASID[CASID]
8.8.12.5 DMMU RAM Entry Read Register 0 (MD_RAM0)
The DMMU RAM entry read register 0 (MD_RAM0), shown in
number and page attributes of an entry indexed by MD_CTR[DTLB_INDX]. This register is updated
when any value is written to MD_CAM.
0
Field
Reset
R/W
16
Field RPN
Reset
R/W
SPR
Figure 8-21. DMMU RAM Entry Read Register 0 (MD_RAM0)
Table 8-21 describes MD_RAM0 fields.
Bits Name
0–19 RPN Real (physical) page number
20–22 PS Page size. (Values not shown are reserved)
000 4 Kbyte
001 16 Kbyte
011 512 Kbyte
111 8 Mbyte
23–26 APGI Access protection group inverted. Access protection group number in one's complement format
27 G Guarded memory attribute for the entry
0 Nonguarded memory
1 Guarded memory
8-28
Table 8-20. MD_CAM Field Descriptions (continued)
19 20 22
PS
Table 8-21. MD_RAM0 Field Descriptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Figure 8-21, contains the physical page
RPN
—
R
23 26 27
APGI G
—
R/W
825
Description
15
28 29 30 31
WT CI —
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