Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 865

Table 31-8 describes the USMOD register fields.
Bits Name
0 LSS
1 RESUME
2–3 —
4 SFTE
5 TEST
6 HOST
7 EN
31.11.2 USB Slave Address Register (USADR)
The USB slave address register is an 8-bit, memory mapped register. It holds the address for this USB port
when operating as a function.
Field
Reset
R/W
Addr
Table 31-9 describes the USADR field.
Bits Name
0 —
1–7 SAD x
Freescale Semiconductor
Table 31-8. USMOD Fields
Low-speed signaling. Selects the signaling speed. The actual bit rate depends on the USB
clock source.
0 Full-speed (12 Mbps) signaling. Normal operation.
1 Low-speed (1.5 Mbps) signaling. For a point-to-point connection with a low-speed device
or for local loopback testing.
Generate resume condition. When set, this bit generates a resume condition on the USB.
This bit should be used if the function wants to exit the suspend state.
Reserved, should be cleared.
0 The external interrupt from the I/O passes through to the CPM controller
1 Timer1 is used to generate the SOF signal. The events from this timer are used as the
CPM external interrupt instead of the signal that arrives from the I/O.
USB controller test(loopback) mode
0 Test mode is disabled
1 Test mode is enabled
Note: This bit may be set only when HOST is set (USB host mode)
USB host mode
0 USB host disabled.
1 USB host is enabled
Enable USB. When the EN bit is cleared, the USB is in a reset state
0 USB is disabled
1 USB is enabled.
Note: Other bits of the USMOD should not be modified by the user while EN is set.
Figure 31-13 shows the USADR.
0 1
—
Figure 31-13. USB Slave Address Register (USADR)
Table 31-9. USADR Fields
Reserved, should be cleared.
Slave address 0–6. Holds the slave address for the USB port, when configured as a function
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
SAD x
0000_0000
R/W
0xA01
Description
Universal Serial Bus (USB)
7
31-17