Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 817

SMCLK
SMSYN
SMTXD
TEN set
here
SMCLK
SMSYN
SMRXD
REN set SMSYN
here or detected
low here
ENTER HUNT
MODE
command
issued
If both SMCMR[REN] and SMCMR[TEN] are set, the first falling edge of SMSYN causes both the
transmitter and receiver to achieve synchronization. The SMC transmitter can be disabled and reenabled
and SMSYN can be used again to resynchronize the transmitter itself.
On the Fly," describes how to safely disable and reenable the SMC. Simply clearing and setting TEN may
be insufficient. The receiver can also be resynchronized this way.
29.4.6 Using TSA for Synchronization
The TSA offers an alternative to using SMSYN to internally synchronize the SMC channel. This method
is similar, except that the synchronization event is the first time-slot for this SMC receiver/transmitter after
the frame sync indication rather than the falling edge of SMSYN.
how to configure time slots. The TSA allows the SMC receiver and transmitter to be enabled
simultaneously and synchronized separately; SMSYN does not provide this capability.
shows synchronization using the TSA.
Freescale Semiconductor
1s are sent Five 1s are sent
SMSYN Tx FIFO Five 1s
detected loaded assume
low here approximately character
here length
equals 5
First bit
of receive NOTES:
1. SMCLK is an internal clock derived from an external
data
CLK x or a baud rate generator.
(lsb)
2. This example shows the SMC receiver and transmitter
enabled separately. If the REN and TEN bits were set at
the same time, a single falling edge of SMSYN would
synchronize both.
Figure 29-11. Synchronization with SMSYN x
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Serial Management Controllers (SMCs)
SMC1 Transmit Data
First bit of Transmission
first 5-bit could begin
transmit here if Tx FIFO
character not loaded
(lsb)
SMC1 Receive Data
Section 29.2.4, "Disabling SMCs
Chapter 20, "Serial Interface,"
in time
describes
Figure 29-12
29-23