Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 153

Powerquicc family

Table of Contents

Table 3-2. Bus Cycles Needed for Single-Register Load/Store Accesses (continued)

Transfer Size

Transfer Address (Last Two Bits)

Atomic Update Primitives

The lwarx and stwcx. instructions are atomic update primitives that set and clear memory reservations.

Reservation accesses made by the same processor are implemented by the LSU. The external bus interface

implements memory reservations as they relate to accesses made by external bus devices. Accesses made

by other internal devices to internal memories implement memory reservations as they relate to special

internal bus snoop logic.

When an lwarx instruction executes, the LSU issues a cycle to the data cache with a special attribute. For

external memory accesses, this attribute causes the external bus interface to set a memory reservation

during the address tenure. External logic must then snoop the external bus to determine if another device

breaks the memory reservation by accessing the same location. KR and CR signals are available to external

logic to signal loss of a reservation to the external bus interface. When an stwcx. instruction addresses

external memory and the external bus interface determines that the reservation was lost, it blocks the

external bus access and notifies the LSU.

The MPC885 supports the memory reservation mechanism in a hierarchical bus structure. For reservations

on internal memory, an lwarx causes on-chip snoop logic to latch the address. This logic notifies the LSU

of any internal master store access and resets the reservation. If a new lwarx instruction address tenure

executes successfully, it replaces any previous reservation address at the appropriate snoop logic.

However, executing an stwcx. instruction cancels the reservation unless an alignment exception is

Freescale Semiconductor

Number of Bus Cycles

MPC885 PowerQUICC Family Reference Manual, Rev. 2

Transfer Type

The MPC8xx Core

Address/Size

0x00/halfword

0x02/halfword

0x02/halfword

0x02/halfword

0x04/halfword

0x04/halfword