Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 798

Serial Management Controllers (SMCs)
Bits Name
6 PEN Parity enable. (UART)
0 No parity.
1 Parity is enabled for the transmitter and receiver as determined by the PM bit.
BS Byte sequence (transparent). For a character length greater than 8 bits, BS controls the byte
transmission sequence if REVD is set. Clear BS to maintain compatibility with MC68360 QUICC.
0 Normal mode. Should be selected if the character length is not larger than 8 bits.
1 Transmit lower address byte first.
— Reserved, should be cleared. (GCI)
7 PM Parity mode. (UART)
0 Odd parity.
1 Even parity.
REVD Reverse data. (transparent)
0 Normal mode.
1 Reverse the character bit order. The msb is sent first.
C# SCIT channel number. (GCI)
0 SCIT channel 0
1 SCIT channel 1. Required for Siemens ARCOFI and SGS S/T chips.
8–9 — Reserved, should be cleared
10–11 SM SMC mode.
00 GCI or SCIT support.
01 Reserved.
10 UART (must be selected for SMC UART operation).
11 Totally transparent operation.
12–13 DM Diagnostic mode.
00 Normal operation.
01 Local loopback mode.
10 Echo mode.
11 Reserved.
14 TEN SMC transmit enable.
0 SMC transmitter disabled.
1 SMC transmitter enabled.
15 REN SMC receive enable.
0 SMC receiver disabled.
1 SMC receiver enabled.
29.2.2 SMC Buffer Descriptors (BDs)
In UART and transparent modes, the SMC memory structure is like the SCC in that SMC-associated data
is stored in buffers. Each buffer is referenced by a BD and organized in a BD table located in the dual-port
RAM. See Figure 29-3.
29-4
Table 29-1. SMCMR Field Descriptions (continued)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Freescale Semiconductor